Abstract: A high speed inverter circuit is disclosed. The inverter has a quiescent state, a set state for receiving an input pulse and generating a set pulse in response thereto, a reset stage in which a delayed version of the same input pulse is used to reset the inverter, and a recovery state for preparing the inverter for the arrival of a new input pulse. The inverter has an extremely fast switching speed because virtually all of the available energy of the input signal is used to set the inverter. The inverter may be used in an inverter chain for rapidly propagating electrical signals.

Abstract: There is disclosed a data input/output control circuit comprising: an input/output circuit for carrying out input of data from the exterior or output of data thereto; and an output circuit such that when the input/output circuit carries out output of data, it delivers, to the input/output circuit, data generated in the exterior and transferred by way of a signal line, while when the input/output circuit carries out input of data, it allows the node between the input/output circuit and the signal line to be placed in high impedance state. In this control circuit, the output circuit includes a switching element and a discharge element connected in series between the signal line and the input/output circuit. The switching element is operative in such a manner that when the input/output circuit carries out output of data, it is closed, while when the input/output circuit carries out input of data, it is opened.

Abstract: A level shifting circuit which can be implemented as part of a bipolar ECL integrated circuit, provides reliable switching and level shifted output suitable for driving a low voltage CMOS integrated circuit. The circuit includes a level shifting circuit which is connected to trigger a high gain positive feedback bootstrap circuit to reliably ensure switching even under poor signal conditions. An output taken from one of the switched pair is allowed to go to V.sub.CC, 0 volts, or is clamped by a clamping circuit to -3.3 volts, representing the two output states suitable for driving inverted rail CMOS circuitry.

Abstract: A digital logic circuit for use in or as a macrocell which can be programmed to operate as a flip-flop or as a latch, or to be transparent to a signal, and which also has programmable output polarity. This programmable macrocell circuit has two master latch elements and one slave latch element. The master latch elements are respectively inverting and noninverting latches which are located on two parallel alternate paths. A set of pass transistors on the input end of the two paths causes an input signal to drive only a selected one of the two paths and its associated master latch element. A two-by-one multiplexer connects the output of the selected master latch element in one of the two signal paths to the input of the slave latch.

Abstract: A base cell for a CMOS gate array is provided with a first plurality of N-channel transistors 12, 14, 16 with two such N-channel transistors coupled in series. A first plurality of P-channel transistors 50, 52, 54 with two such P-channel transistors coupled in series. These transistors are interconnected at the transistor level to form a partially prewired circuit. Additional pairs of series connected N-channel transistors (18, 20), (22, 24) and pairs of series connected P-channel transistors (56, 58), (60, 62) are also provided and are interconnected at the transistor level to form additional partially prewired circuits. By adding additional levels of wiring 100, 102, the base cell can be finally wired to form a plurality of different logic circuits.

Abstract: A fuse, having reduced blow-current requirements thereby minimizing the power supply voltage and chip area required for the driver transistors, has a geometry which is characterized by an essentially uniform width dimension throughout the primary axis of the fuse link but having at least one approximately right angle bend in the fuse link. The fuse can be blown open with approximately 10% of the input current density required for a straight fuse of equal cross-sectional area. The reason for this is that, due to current crowding, the current density is accentuated at the inside corner of the bend. As the input current to the fuse is increased, a current density is reached at the inside corner which causes the fuse material to melt. A notch forms at the inside corner. The fuse geometry altered by the notching causes even more severe current crowding at the notches, and this in turn makes the melting propagate across the width of the fuse.

Abstract: A complete logic family which is SEU immune is constructed, using logic/circuit design techniques, to recover from an SEU, regardless of the shape of the upsetting event. The logic family provides a redundancy of data to be used to restore data lost by an SEU. Two transistor networks are used, a p-channel network and an n-channel network. Each transistor network consists of a plurality of input transistors and a feedback transistor. The feedback transistor is sized to be weak compared to the input transistors. The transistor networks are designed to either resist an SEU or to shutdown until the SEU is over and then the network which is not shutdown will restore the data of the network that was hit by the SEU. The logic family can prevent glitch propagation from an upset node and can be implemented in a standard, commercial CMOS process without any additional processing steps. The logic family includes but is not limited to an Inverter, 2-input Nand, 2-input Nor, 3-input OrNand and a 3-input AndNor.

Abstract: A CMOS differential twisted-pair driver which utilizes CMOS switches and current sources advantageously. No alternative power supply is required, the switches do not have to be low impedance and the device is low power. The preferred embodiment driver further limits signal overshoot and common mode energy. The signal transmission facility is bi-directional so an off state is provided. It is doubly terminated to provide for symmetry, improved bandwidth and reduces reflective signal noise. The double termination also provides for faster rise and fall times which reduces the systems sensitivity to receiver offset.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a plurality of logic cells ("modules") integrated with the programmable configuration network. Each logic cell is a powerful general purpose universal logic building block. Each logic cell consists essentially of four two-input AND gates, one or two six-input AND gates, three multiplexers, and a D-type flipflop.

Abstract: An output circuit is intended to be connected to any one of the circuits of a positive logic and a negative logic without having to initialize such a device as a register connected thereto. The output circuit is arranged to output a signal from a first logic circuit to a second logic circuit so that the first logic circuit is connected to an internal input terminal and the second logic circuit is connected to an external output terminal of the output circuit. The output circuit includes a logic state checking unit, a state storing unit, and a logic converting unit. The logic state checking unit serves to check the logic state of the external output terminal when initializing the first logic circuit. The state storing unit stores the checked logic state. The logic converting unit serves to compare the stored logic state of the output terminal with a logic state of a signal at the input terminal sent from the first logic circuit and determine the logic level of a signal to be fed to the second logic circuit.

Abstract: A set of signal buffering circuits for driving heavily loaded signal lines. The buffer circuits detect a signal transition before the signal reaches logical threshold levels, and help drive the signal in the detected transition direction. The early transition detection and drive help reduce signal propagation delay across heavily loaded lines.

Abstract: An input buffer circuit with first and second inverters serially connected between an input terminal and an output terminal of the circuit. The input buffer circuit includes a level detector circuit for detecting that the level of a signal inputted to the input terminal is logically unsteady, and an output level holding circuit for detecting the level of a node where the first and second inverters are connected together and controlling the level of the node to maintain the level, when the level detector circuit detects that the level of the signal is logically unsteady.

Abstract: A CMOS circuit for converting voltage levels between shifted differential ECL voltage level input signals and a CMOS voltage level signal. The ECL levels are referenced to the VDD voltage of the CMOS circuit and can be connected to ECL circuits that are connected between the CMOS VDD voltage and ground. The circuit has a pFET connected between a supply voltage and the output signal, and an nFET connected between the output signal and circuit ground. An inverted signal of the differential shifted ECL voltage input signals is connected to a gate of the nFET. A level shifting circuit connects the input signals to a gate of the pFET to ensure that it correctly drives the output signal when the input signals change logic levels.

Abstract: A chip can be provide with circuits to electrically read, blow and latch fuses. The circuit allows use of existing I/O pads used for other functions on a chip to drastically reduce the number of I/O required to blow fuses. The circuits also share critical high current carrying lines with no impact on fuse functionality and device reliability. By offering of complex fuse operations such as electrical override, even after they had been blown, essential for product screening and product diagnostics. The circuit provides a fuse blow circuit fed by a fuse sense circuit and fuse latch circuit. Stored addresses in an address buffer addresses the fuses with two sets of inputs: one providing electrical override and/or fuse blow information; and the second one, normal fuse status. Fuse integrity before and after blow is maximized with a dual voltage source drive and low current sensing.

Abstract: A highly reliable, large fan-in, high speed, BiCMOS circuit. The amount of MOS transistor parasitic capacitance appearing on the output line of the circuit is reduced by adding only emitter capacitance of bipolar transistors to the output line for each input to the basic logic circuit. Circuitry is provided to raise the base voltage of a reverse biased bipolar transistors to reduce or eliminate the reverse bias.

Abstract: In accordance with the teachings of this invention, a novel interface circuit is incorporated in a lower voltage circuit, allowing that circuit to properly interface with a higher voltage bus even when the lower voltage circuit is powered down. In accordance with the teachings of this invention, a pass transistor is used which connects the lower voltage circuit to the bus during normal operation, and which disconnects the lower voltage circuit from a bus when desired, such as when the lower voltage circuit is powered down. Additional circuit means are provided to ensure that the voltage across the pass transistor does not exceed a safe level, such as by utilizing voltage divider circuitry for dividing the bus voltage so that only a portion of the bus voltage appears across the pass transistor. In one embodiment of this invention, the voltage divider is formed of resistors, diodes, load devices, or combinations thereof.

Abstract: There is disclosed a semiconductor integrated circuit comprising pass transistor circuits (PT3, PT4) for producing logically complementary signals. The output of the pass transistor circuit (PT3) is connected to the base electrode of an NPN bipolar transistor (BN1), and the output of the pass transistor circuit (PT4) is connected to the gate electrode of an NMOS transistor (MN9). PMOS transistors (MP15, MP16) are connected between the outputs of the pass transistor circuits (PT3, PT4) and a first potential (VDD). The gate electrodes of the PMOS transistors (MP15, MP16) are connected to the outputs of the pass transistor circuits (PT3, PT4). The bipolar transistor (BN1) having a large driving force charges and discharges a load capacity (CL1) connected to an output terminal in response to the output signal of the pass transistor circuit (PT3). This provides for a logic circuit which operates at high speeds in the semiconductor integrated circuit.

Abstract: A current mode logic switching stage, especially an output stage for driving capacitive loads, includes a differential amplifier configuration and at least two bipolar transistors, which are connected as an emitter follower circuit to the output of the differential amplifier configuration. The emitter of one of the bipolar transistors is connected with an output of the switching stage. A controllable current source, which is controlled by a comparison device, is connected between the output and a negative supply potential. The comparison device receives emitter signals of the bipolar transistors. The current source is controlled in such a way that it impresses a high current only during a negative output signal edge. The comparison device is formed with a current mirror.

Abstract: A field programmable gate array (FPGA) includes a distributed switch matrix for programmably connecting the various routing conductors. The distributed switch matrix comprises groups of additional conductors, referred to as "Switching R-nodes". The Switching R-nodes programmably connect selected ones of the (e.g, horizontal) routing conductors to other selected ones of the (e.g., vertical) routing conductors. In this manner, the direct connection between the routing conductors may be avoided, allowing for a reduced number of programmable interconnect devices. In one preferred embodiment, a nibble-mode architecture is used, wherein four data conductors are provided for each group of routing conductors, with other multiples-of-four data conductors also being advantageous.

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.