Patents Examined by Andrew Tran
  • Patent number: 6300175
    Abstract: A method of fabricating a thin film transistor includes crystallizing an amorphous silicon layer having a sloping surface and a flat surface by an SLS technique using a laser beam having predetermined energy density so as to melt the sloping surface as well as the flat surface of the amorphous silicon layer to form a crystallized silicon layer and forming the active layer by selectively etching the crystallized silicon layer. The laser beam is applied non-vertically to the sloping surface while the laser beam is applied vertically to the flat surface. Although the sloping surface and the flat surface of the amorphous silicon layer are irradiated with a laser beam having the same laser energy density, the absorbed energy density of the sloping surface may be lower than that of the flat surface. The laser beam generates a first energy density to substantially melt the sloping surface and a second energy density to substantially melt the flat surface of the amorphous silicon.
    Type: Grant
    Filed: May 13, 1999
    Date of Patent: October 9, 2001
    Assignee: LG. Philips LCD., Co., Ltd.
    Inventor: Dae-Gyu Moon
  • Patent number: 6291312
    Abstract: A method for forming a pullback opening above a shallow trench isolation structure. A patterned mask layer is formed over a substrate. A sacrificial layer is formed on the sidewalls of the mask layer. The exposed portion of the substrate is etched to form a trench in the substrate. The sacrificial layer is removed to increase the width of the opening above the trench.
    Type: Grant
    Filed: September 14, 1999
    Date of Patent: September 18, 2001
    Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.
    Inventors: Bor-Wen Chan, Yuan-Hung Liu
  • Patent number: 6287884
    Abstract: A buried hetero-structure with native oxidized current blocking layer for InP-based opto-electronic devices comprises a InP semiconductor substrate, a buffer layer, a ridge mesa containing lower confinement layer, active layer and upper grating confinement layer, a first InP cladding layer and a native oxidized Al-bearing layer as current blocking layers at both lateral edges, a second InP cladding layer, contact layer, contact metal, and the second ridge mesa covered with insulating layer. This method is to facilitate the processing of conventional buried hetero-structure InP-based opto-electronic device and improve the performance under high temperature and high current operation.
    Type: Grant
    Filed: January 20, 1999
    Date of Patent: September 11, 2001
    Assignee: Institute of Materials Research and Engineering
    Inventors: Wang Zhi Jie, Chua Soo Jin
  • Patent number: 6268268
    Abstract: A method of manufacturing a semiconductor device comprises the steps of: (a) forming a first oxide film and a first silicon nitride film on a surface semiconductor layer of an SOI substrate, the SOI substrate comprising the surface semiconductor layer formed on a support substrate with the intervention of a buried insulating film; (b) patterning the first silicon nitride film into a desired shape and performing a first LOCOS oxidization using the thus patterned first silicon nitride film as a mask to form a first LOCOS oxide film in a region for device isolation in the surface semiconductor layer; (c) selectively removing the first LOCOS oxide film, (d) forming sidewall spacers of a second silicon nitride film on sidewalls of the first silicon nitride film and the first oxide film; (e) performing a second LOCOS oxidization using the first silicon nitride film and the sidewall spacers as a mask to form a second LOCOS oxide film which is thinner than the first LOCOS oxide film; and (f) removing the first and se
    Type: Grant
    Filed: September 22, 2000
    Date of Patent: July 31, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Nobuaki Tokushige
  • Patent number: 6261868
    Abstract: A method for packaging a semiconductor device (23) to form a semiconductor component (10). A die attach material (17) is disposed on a flange (11). A semiconductor chip (23) is bonded to the die attach material (17). After disposing the die attach material (17) on the flange (11), an insulator material (28) is coupled to the flange (11). A leadframe (32) is coupled to the semiconductor chip (23) via a plurality of wirebonds (36). The wirebonds (36) and the semiconductor chip (23) are protected by a lid (37).
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: July 17, 2001
    Assignee: Motorola, Inc.
    Inventors: Gerald R. Miller, Lakshminarayan Viswanathan
  • Patent number: 6221719
    Abstract: Process for the manufacturing of a DMOS-technology transistor, providing for forming, over a semiconductor material layer of a first conductivity type, an insulated gate electrode, introducing in said semiconductor material layer a first dopant of a second conductivity type for forming at least one body region of a second conductivity type extending under the insulated gate electrode, and introducing in said at least one body region a second dopant of the first conductivity type for forming, inside said body region, at least one source region of the first conductivity type, said body region and said source region defining, under the insulated gate electrode, a channel region for the DMOS transistor, wherein said first dopant is aluminum. After the introduction of said first dopant and said second dopant, a single thermal diffusion process for simultaneously diffusing the first dopant and the second dopant is provided.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: April 24, 2001
    Assignee: STMicroelectronics S.r.l.
    Inventor: Giovanni Franco
  • Patent number: 6215693
    Abstract: Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: April 10, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeon-bae Chung, Byung-gil Jeon
  • Patent number: 6208551
    Abstract: A DRAM made in monolithic form, the cells of which each include a MOS transistor and a capacitor, a second electrode of which is common to all cells of a same row and is covered with an insulator, the insulator being coated with independent conductive elements distributed on a same horizontal plane, two neighboring elements being biased to respective high and low levels.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: March 27, 2001
    Assignee: STMicroelectronics S.A.
    Inventors: Hervé Jaouen, Richard Ferrant
  • Patent number: 6207469
    Abstract: A GaN type semiconductor layer in which a group 2 impurity element is added is formed. The GaN type semiconductor layer is heated at a predetermined temperature, while irradiating the semiconductor layer with an electromagnetic wave having an energy larger than the band gap energy of the GaN type semiconductor layer.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: March 27, 2001
    Assignee: Pioneer Electronic Corporation
    Inventors: Hiroyuki Ota, Yoshinori Kimura, Mamoru Miyachi
  • Patent number: 6184686
    Abstract: A method and apparatus for detecting a contaminant in a substrate. An array of anode elements is positioned in proximity to the substrate and is biased at a positive voltage relative to the substrate. The substrate is irradiated with photons having energies below an atomic ionization energy of the substrate, so as to ionize the contaminant to emit electrons. The emitted electrons are collected at one or more of the anode elements, thereby generating a current indicative of the presence of the contaminant in the semiconductor in proximity to the one or more of the anode elements.
    Type: Grant
    Filed: July 13, 1998
    Date of Patent: February 6, 2001
    Assignee: Jordan Valley Applied Radiation Ltd.
    Inventors: Isaac Mazor, Amos Gvirtzman, Reuven Duer
  • Patent number: 6168981
    Abstract: A method and apparatus for the localized reduction of the lifetime of charge carriers in integrated electronic devices. The method comprises the step of implanting ions, at a high dosage and at a high energy level, of a noble gas, preferably helium, in the active regions of the integrated device so that the ions form bubbles in the active regions. A further thermal treatment is performed after the formation of bubbles of the noble gas in order to improve the structure of the bubbles and to make the noble gas evaporate, leaving cavities in the active regions.
    Type: Grant
    Filed: January 6, 1999
    Date of Patent: January 2, 2001
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Anna Battaglia, Piergiorgio Fallica, Cesare Ronsisvalle, Salvatore Coffa, Vito Raineri
  • Patent number: 6162650
    Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 19, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Satyendra Sethi
  • Patent number: 6159784
    Abstract: A method of producing a semiconductor device by which the resistivities of the base, collector, and source/drain regions in a Bi-CMOS are decreased and the production step is simplified. A method of producing a semiconductor device comprising the steps of forming a gate electrode (the first semiconductor layer) on a substrate; forming an insulating film; forming a second semiconductor layer; leaving the second semiconductor layer and the insulating film on the bipolar part and removing them on the CMOS part to form sidewalls on the side faces of the gate electrode; forming source/drain regions; forming a Ti layer over the entire surface and forming silicide on the surfaces of the second semiconductor layer, the source/drain regions, and the gate electrode; and forming a base electrode by patterning the second semiconductor layer.
    Type: Grant
    Filed: June 14, 1999
    Date of Patent: December 12, 2000
    Assignee: Sony Corporation
    Inventors: Hiroaki Ammo, Hiroyuki Miwa
  • Patent number: 6156583
    Abstract: A method of manufacturing an LCD requires only 4 masking while preventing undercutting of a semiconductor layer and includes the steps of etching a passivation layer, an a-Si layer and a gate insulating layer simultaneously by using CF.sub.4 /He gas. The flow ratio of the He gas to CF.sub.4 gas is preferably about 15% to about 35%.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: December 5, 2000
    Assignee: LG Philips LCD Co., Ltd.
    Inventor: Kwang Jo Hwang
  • Patent number: 6153449
    Abstract: A method for creating hermetic seals in semiconductor packages is provided. The method includes the applying a sealing glass to ceramic layers and placing a ceramic tape layer there between. The assemblage is then laminated and fired, or sintered, to marry the material layers together to form a hermetic seal. The hermetic seal made thereby may be incorporated into a wide variety of semiconductor devices including packages and feedthroughs.
    Type: Grant
    Filed: April 24, 1998
    Date of Patent: November 28, 2000
    Assignee: Brush Wellman Inc.
    Inventors: Larry G. Yglesia, Joseph S. Occhipinti, Clark M. Steddom
  • Patent number: 6147889
    Abstract: A high memory capacity with relatively low demands on the optical quality of the components used is possible in accordance with the invention by the means to generate the at least two light rays and/or the memory element and/or means to guide the light rays are designed in such a way that the spatial orientation of the interference sample generated in the memory element by the light rays can be changed in any spatial direction over the spatial orientation of an interference pattern stored in the memory element and/or a light diffracting structure present in the memory element. The invention further relates to a device for the readout of optical information and a method for the optical recording and for the optical readout of information.
    Type: Grant
    Filed: January 15, 1999
    Date of Patent: November 14, 2000
    Assignee: CAMPus Technologies AG
    Inventor: Thilo Weitzel
  • Patent number: 6133073
    Abstract: The present invention is related to a thin film semiconductor which can be regarded as substantially a single crystal and a semiconductor device comprising an active layer formed by the thin film semiconductor. At least a concave or convex pattern is formed intentionally on a insulating film provided in contact with the lower surface of an amorphous silicon film, whereby at least a site is formed in which a metal element for accelerating crystallization can be segregated. Therefore, a crystal nuclei is selectively formed in a portion where the concave or convex pattern is located, which carries out controlling a crystal diameter. Thus, a crystalline silicon film is obtained. A crystallinity of the crystalline silicon film is improved by the irradiation of a laser light or an intense light having an energy equivalent to that of the laser light, whereby a monodomain region in which no grain boundary substantially exit is formed.
    Type: Grant
    Filed: April 23, 1998
    Date of Patent: October 17, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Jun Koyama, Takeshi Fukunaga
  • Patent number: 6127209
    Abstract: A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode.
    Type: Grant
    Filed: April 21, 1999
    Date of Patent: October 3, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigenobu Maeda, Yasuo Yamaguchi, Hirotada Kuriyama, Shigeto Maegawa
  • Patent number: 6122207
    Abstract: A semiconductor memory device includes a plurality of memory cell groups, the data for the plurality of memory cell groups being transmitted through mutually different buses, and a redundancy memory cell group common to the plurality of memory cell groups. The semiconductor memory device further includes a control circuit for transmitting data for one or more memory cells of the redundancy memory cell group in place of data for one or more defective memory cells in any of the plurality of memory cell groups. Each of the plurality of memory cell groups is provided corresponding to every different input/output terminal of the memory device, or the plurality of memory cell groups are provided corresponding to a common input/output terminal of the memory device.
    Type: Grant
    Filed: March 16, 1999
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventors: Yasuji Koshikawa, Tomoko Nobutoki, Kouji Mine
  • Patent number: 6118729
    Abstract: This invention discloses a synchronous semiconductor memory device based on the DDR scheme. This device includes a memory cell array including first and second memory cell groups, first and second data lines, a data transfer circuit capable of at least respectively connecting memory cells included in the first and second memory cell groups to the first and second data line, a first output transfer circuit for transferring first output data sent to one of the first and second data lines at up-edge and down-edge of an operation clock, a second output transfer circuit for transferring second output data sent to the other of the first and second data lines at the up-edge and down-edge of the operation clock, and a data line control circuit capable of selectively connecting the first data line to one of the first and second output transfer circuits and selectively connecting the second data line to one of the first and second output transfer circuits.
    Type: Grant
    Filed: October 27, 1998
    Date of Patent: September 12, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Osamu Hirabayashi, Atsushi Kawasumi