Abstract: A power semiconductor device includes: a plurality of power modules including control terminals; a heat sink, on which the plurality of power modules are mounted; and a control substrate, to which the control terminals are fixed. The plurality of power modules each include a first protruding portion close to the control terminals, and a second protruding portion far from the control terminals. The heat sink has, at a position corresponding to the first protruding portion, a first recessed portion formed to have an inner diameter larger than an outer diameter of the first protruding portion, and engaged with the first protruding portion. At a position corresponding to the second protruding portion, the heat sink has a second recessed portion formed to have the shape of an elongated hole whose minor diameter is larger than an outer diameter of the second protruding portion, and engaged with the second protruding portion.

Abstract: Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a substrate. The semiconductor device also includes a first fin and a second fin over the substrate. The semiconductor device further includes a first gate electrode and a second gate electrode traversing over the first fin and the second fin, respectively. In addition, the semiconductor device includes a gate dielectric layer between the first fin and the first gate electrode and between the second fin and the second gate electrode. Further, the semiconductor device includes a dummy gate electrode over the substrate, and the dummy gate electrode is between the first gate electrode and the second gate electrode. An upper portion of the dummy gate electrode is wider than a lower portion of the dummy gate electrode.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: Technologies for adaptive bandwidth reduction for an Internet of Things (IoT) gateway device are disclosed. The IoT gateway device receives data from one or more sensors, and determines a mathematical model to represent the sensor data. Certain aspects of the mathematical model used, such as the quantity of coefficients and the precision of the coefficients are determined based on the sensor data. For example, if the sensor data is within a normal range, a relatively small number of coefficients might be used, but if the sensor data is past or near an alert threshold, a larger number of coefficients might be used, which allows for the behavior of the sensor data to be better represented.

Abstract: A method for manufacturing a ferromagnetic-dielectric composite material comprises: (a) placing patterned ferromagnetic layer regions, in a patterning substrate assembly that includes a patterning substrate and a first dielectric layer, in physical contact with a second dielectric layer, the second dielectric layer in a receiving substrate assembly that includes a receiving substrate, (b) forming a bond between the patterned ferromagnetic layer regions and the second dielectric layer; (c) releasing the patterning substrate from the patterning substrate assembly to transfer the patterned ferromagnetic layer regions and the first dielectric layer from the patterning substrate assembly to the receiving substrate assembly; and (d) releasing the receiving substrate from the receiving substrate assembly to form the ferromagnetic-dielectric composite material.

Abstract: Through-dielectric-vias (TDVs) for 3D integrated circuits in silicon are provided. Example structures and processes fabricate conductive vertical pillars for an integrated circuit assembly in a volume of dielectric material instead of in silicon. For example, a block of a silicon substrate may be removed and replaced with dielectric material, and then a plurality of the conductive pillars can be fabricated through the dielectric block. The through-dielectric-vias are shielded from devices and from each other by an intervening thickness of the dielectric sufficient to reduce noise, signal coupling, and frequency losses.

Abstract: A touch array substrate and a manufacturing method thereof, wherein in the touch array substrate, an active layer, an insulating layer, a pixel electrode layer, a metal layer, a planarization layer, and a common electrode layer are sequentially disposed on the buffer layer. The active layer includes a first region corresponding to a source electrode and a second region corresponding to a drain electrode. The pixel electrode layer includes a plurality of base layers. The metal layer is correspondingly disposed on the base layers. The metal layer includes a touch signal line, a data line, and a gate electrode. The common electrode layer includes a touch electrode, the source electrode, and the drain electrode.

Abstract: An integrated circuit package includes a leadframe with a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. A clip has a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

Abstract: A thyristor tile includes first and second PNP tiles and first and second NPN tiles. Each PNP tile is adjacent to both NPN tiles, and each NPN tile is adjacent to both PNP tiles. A thyristor includes a plurality of PNP tiles and a plurality of NPN tiles. The PNP and NPN tiles are arranged in an alternating configuration in both rows and columns. The PNP tiles are oriented perpendicular to the NPN tiles. Interconnect layers have a geometry that enables even distribution of signals to the PNP and NPN tiles.

Abstract: A semiconductor structure and method of forming the same are provided. The method includes: forming a plurality of mandrel patterns over a dielectric layer; forming a first spacer and a second spacer on sidewalls of the plurality of mandrel patterns, wherein a first width of the first spacer is larger than a second width of the second spacer; removing the plurality of mandrel patterns; patterning the dielectric layer using the first spacer and the second spacer as a patterning mask; and forming conductive lines laterally aside the dielectric layer.

Abstract: A light-emitting device and a display apparatus including the same are provided. The light-emitting device includes a metal reflective layer having a phase modulation surface, a first electrode on the metal reflective layer, an organic emission layer which is provided on the first electrode and emits white light, and a second electrode on the organic emission layer. The phase modulation surface includes a plurality of protrusions and a plurality of recesses.

Abstract: A display apparatus includes a display module including a display surface. The display module includes a display panel including a plurality of display devices which displays an image on the display surface, a plurality of light concentration lenses arranged on the display panel, a buffer layer disposed on the light concentration lenses, and a plurality of diffraction patterns arranged at regular intervals on the buffer layer, where the diffraction patterns diffract a portion of lights incident thereto.

Abstract: A coating liquid for forming an n-type oxide semiconductor film, the coating liquid including: a Group A element, which is at least one selected from the group consisting of Sc, Y, Ln, B, Al, and Ga; a Group B element, which is at least one of In and Tl; a Group C element, which is at least one selected from the group consisting of Group 4 elements, Group 5 elements, Group 6 elements, Group 7 elements, Group 8 elements, Group 9 elements, Group 10 elements, Group 14 elements, Group 15 elements, and Group 16 elements; and a solvent.

Abstract: The disclosure provides a display substrate and a manufacturing method thereof, a display panel and a display apparatus. The display substrate includes a substrate and an electroluminescent layer on the substrate. The display substrate further includes a first reflective electrode layer, a buffer layer and a second reflective electrode layer sequentially formed on a side of the electroluminescent layer distal to the substrate. The buffer layer is provided with a first hollow region, the second reflective electrode layer is provided with a second hollow region, an overlapping region between the first hollow region and the second hollow region is configured to transmit light emitted by the electroluminescent layer. The present disclosure can detect the light-emitting brightness of each sub-pixel in the organic electroluminescent layer in real time to improve light-emitting efficiency.

Abstract: Carrier with an electrically insulating base material, electrically conductive through-connections and a thermal connection element. The through-connections and the thermal connection element are each completely surrounded by the base material in the lateral direction, the thermal connection element and the through-connections completely penetrating the base material perpendicularly to the main extension plane of the carrier, and the thermal connection element being formed with a material which has a thermal conductivity of at least 200 W/(m K).

Abstract: A method of manufacturing a glass article comprising: forming a first layer of a first metal on a glass substrate, the glass substrate comprising silicon dioxide and aluminum oxide; subjecting the glass substrate with the first layer of the first metal to a first thermal treatment; forming a second layer of a second metal over the first layer of the first metal; and subjecting the second layer of the second metal to a second thermal treatment, the first thermal treatment and the second thermal treatment inducing intermixing of the first metal, the second metal, and at least one of aluminum, aluminum oxide, silicon, and silicon dioxide of the glass substrate to form a metallic region comprising the first metal, the second metal, aluminum oxide, and silicon dioxide. The first metal can be silver. The second metal can be copper.

Abstract: A display panel and a display device are provided. The display panel includes a substrate, a driving circuit layer, a planarization layer, and a light-emitting unit layer. The driving circuit layer is provided on a side of the substrate. The planarization layer is provided on a side of the driving circuit layer facing away from the substrate. The light-emitting unit layer is provided on a side of the planarization layer facing away from the driving circuit layer. The planarization layer includes a first planarization sublayer and a second planarization sublayer. The first planarization sublayer is arranged at least in a first region of the display panel. The second planarization sublayer is arranged at least in a second region of the display panel. Materials of the first planarization sublayer and the second planarization sublayer are different in composition.

Abstract: A display apparatus includes a substrate, a first thin-film transistor including a first semiconductor layer on the substrate, and a first gate electrode on the first semiconductor layer, the first gate electrode being insulated from the first semiconductor layer by a first gate insulating layer, an organic interlayer insulating layer covering the first gate electrode, a first conductive layer on the organic interlayer insulating layer, a first contact hole exposing a top portion of the first semiconductor layer by penetrating through the organic interlayer insulating layer and the first gate insulating layer, and a first protruding portion protruding from a top surface of the substrate between the substrate and the first semiconductor layer, the first protruding portion corresponding to the first contact hole, wherein the first conductive layer contacts the first semiconductor layer through the first contact hole.

Abstract: A display panel and a display device are provided. The display panel has a display area. The display panel includes: a base substrate; a driving circuit and at least one signal line on the base substrate; and at least one insulating layer between the driving circuit and the at least one signal line. The driving circuit is disposed in a periphery of the display area; and an orthogonal projection of at least one of the signal lines on the base substrate has an overlapping area with an orthogonal projection of the driving circuit on the base substrate.

Abstract: Methods of forming structures including a photoresist underlayer and structures including the photoresist underlayer are disclosed. Exemplary methods include forming the photoresist underlayer that includes metal. Techniques for treating a surface of the photoresist underlayer and/or depositing an additional layer overlying the photoresist underlayer are also disclosed.