Abstract: A vertical MOSFET having a trench gate structure includes an n?-type drift layer and a p-type base layer formed by epitaxial growth. In the n?-type drift layer, an n-type region, an upper second p+-type region, a lower second p+-type region and a first p+-type region are provided. The lower second p+-type region is provided orthogonal to a trench, and a total mathematical area regions that are between the first p+-type region and the p-type base layer and that include the n-type region is at least two times a total mathematical area of regions that are between the first p+-type region and the p-type base layer and that include the upper second p+-type region.

Abstract: Semiconductor devices and methods of formation are provided herein. A semiconductor device includes a first inductor, a patterned ground shielding (PGS) proximate the first inductor comprising one or more portions and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. The semiconductor device also has a configuration including a first inductor on a first side of the PGS, a second inductor on a second side of the PGS and a first switch configured to couple a first portion of the PGS to a second portion of the PGS. Selective coupling of portions of the PGS by activating or deactivating switches alters the behavior of the first inductor, or the behavior and interaction between the first inductor and the second inductor. A mechanism is thus provided for selectively configuring a PGS to control inductive or other properties of a circuit.

Abstract: A light emitting element including at least a first trench portion having an indented shape within a single light emitting region. The first trench portion includes a first electrode, an EL layer, and a second electrode. The first electrode, the EL layer, and the second electrode are layered in this order and in contact with each other. At least one of the first electrode or the second electrode includes a reflective electrode.

Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.

Abstract: Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.

Abstract: The present invention relates to methods and apparatuses for using head waves to greatly improve microseismic event localization accuracy, particularly in the depth dimension, by analyzing them in addition to direct path arrivals whenever they are observed. Embodiments of the invention also include techniques known as multipath analysis.

Abstract: A semiconductor package with an embedded capacitor and corresponding manufacturing methods are described. The semiconductor package with the embedded capacitor includes a semiconductor die having a first metal layer extending across at least a portion of a first side of the semiconductor die and a package structure formed on the first side of the semiconductor die. A first electrical conductor of the embedded capacitor is formed in the first metal layer of the semiconductor die. The package structure includes a second metal layer that has formed therein a second electrical conductor of the embedded capacitor. A dielectric of the embedded capacitor is positioned within either the semiconductor die or the package structure of the semiconductor package to isolate the first electrical conductor from the second electrical conductor of the embedded capacitor.

Abstract: A light-emitting display device includes a pixel defining layer with an opening that exposes a first electrode, a hole injection layer on the first electrode, a lyophilic pattern on the hole injection layer in the opening, a hole transport layer on the lyophilic pattern, a light-emitting layer on the hole transport layer, and a second electrode on the light-emitting layer. The lyophilic pattern includes a first part adjacent to a first sidewall of the opening and a second part adjacent to a second sidewall of the opening. A distance from a top surface of the hole injection layer to an edge of a top surface of the second part corresponds to a first height. A distance from the top surface of the hole injection layer to a top surface of the first part corresponds to a second height. The first height is lower than the second height.

Abstract: An organic electroluminescent device and organic electroluminescent display device having enhanced efficiency are disclosed. The organic electroluminescent device includes first and second electrodes facing each other on a substrate, first and second emission layers formed between the first and second electrodes, a hole transport layer formed between the first electrode and the first emission layer, an electron transport layer formed between the second electrode and the second emission layer, and at least one emission control layer formed between the first and second emission layers and having the same properties as those of at least any one of the hole transport layer and the electron transport layer.

Abstract: A method for forming a replacement metal gate structure sharing a single work function metal for both the N-FET and the P-FET gates. The method oppositely dopes a high-k material of the N-FET and P-FET gate, respectively, using a single lithography step. The doping allows use of a single work function metal which in turn provides more space in the metal gate opening so that a bulk fill material may occupy more volume of the opening resulting in a lower resistance gate.

Abstract: In one embodiment, a semiconductor device includes a substrate, and first to fourth interconnects provided on the substrate to be adjacent to one another. The device includes a first pad portion connected with the first or second interconnect, and a second pad portion adjacent to the first pad portion in a first direction. The device includes a third pad portion connected with the third or fourth interconnect, and adjacent to one of the first and second pad portions in a second direction, and a fourth pad portion adjacent to the third pad portion in the first direction, and adjacent to the other of the first and second pad portions in the second direction. The device includes one or more interconnects insulated from the first to fourth interconnects and the first to fourth pad portions, and provided between the first and second interconnects and the third and fourth interconnects.

Abstract: A stacked interconnect structure includes a first conductive layer, a second conductive layer, and a first dielectric layer disposed between the first and second conductive layers and having an air gap in a portion of the first dielectric layer that separates the first and second conductive layers. A second dielectric layer is parallel to the first conductive layer, a third dielectric layer overlays a portion of the second dielectric layer and contacts two opposing surfaces of the second conductive layer. A first via extends into the air gap of the first dielectric layer, wherein the second conductive layer is separated from the first via by a portion of the third dielectric layer that extends from a given surface of the third dielectric layer to the second dielectric layer, and a second via that extends from the given surface of the third dielectric layer to the second conductive layer.

Abstract: Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Abstract: An organic light-emitting display apparatus includes a thin-film transistor on a substrate, a planarization layer on the thin-film transistor, and a pixel-defining spacer on the planarization layer. The pixel-defining spacer defines a pixel area between two pixels that are adjacent in a first direction.

Abstract: A semiconductor device includes a first semiconductor chip comprising a first metallic structure and a second semiconductor chip comprising a second metallic structure. The second semiconductor chip is bonded with the first semiconductor chip by a conductive material filled in a through via. The through via connects the first metallic structure and the second metallic structure, wherein a portion of the through via is inside the first semiconductor chip and the second semiconductor chip.

Abstract: A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line; forming a second barrier layer in the isolation trench; removing a portion of the second barrier layer from a bottom of the isolation trench exposing the first ILD; and forming a second ILD on the second barrier and in the isolation trench, where a bottom of the second ILD is in the first ILD.

Abstract: A semiconductor device is provided that includes a pedestal of an insulating material present over at least one layer of a semiconductor material, and at least one fin structure in contact with the pedestal of the insulating material. Source and drain region structures are present on opposing sides of the at least one fin structure. At least one of the source and drain region structures includes at least two epitaxial material layers. A first epitaxial material layer is in contact with the at least one layer of semiconductor material. A second epitaxial material layer is in contact with the at least one fin structure. The first epitaxial material layer is separated from the at least one fin structure by the second epitaxial material layer. A gate structure present on the at least one fin structure.

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.