Abstract: A semiconductor device has a DRAM cell configured from an information charge accumulating capacitor and a memory cell selecting transistor, the threshold voltage value of a MOS transistor that constitutes a sense circuit is monitored, and the monitored threshold voltage value of the MOS transistor is converted through the use of a transfer ratio that is determined based on the capacitance of the information charge accumulating capacitor and the parasitic capacitance of the bit line. The converted voltage value is level-shifted so that the pre-charge voltage of a pre-charge circuit is a pre-set voltage, a current feeding capability is added to the level-shifted voltage value, and the voltage is fed as the pre-charge voltage.

Abstract: A system for acquiring an ultrasound signal comprises a signal processing unit adapted for acquiring a received ultrasound signal from an ultrasound transducer having a plurality of elements. The system is adapted to receive ultrasound signals having a frequency of at least 20 megahertz (MHz) with a transducer having a field of view of at least 5.0 millimeters (mm) at a frame rate of at least 20 frames per second (fps). The signal processing can further produce an ultrasound image from the acquired ultrasound signal. The transducer can be a linear array transducer, a phased array transducer, a two-dimensional (2-D) array transducer, or a curved array transducer.

Abstract: The embodiments described herein provide a method and controller for performing a sequence of commands. In one embodiment, a controller receives a command from a host to perform a memory operation in a flash memory device, wherein the command comprises at least one bit that indicates whether the command is a stand-alone command or is part of a sequence of commands. The controller analyzes the at least one bit to determine whether the at least one bit indicates that the command is a stand-alone command or is part of a sequence of commands. If the at least one bit indicates that the command is a stand-alone command, the controller performs the command. If the at least one bit indicates that the command is part of a sequence of commands, the controller performs the command as part of the sequence of commands.

Abstract: A semiconductor memory having a memory cell structure capable of reducing soft error without complicating a circuit configuration. Specifically, an inverter (I1) consists of a NMOS transistor (N1) and a PMOS transistor (P1), and an inverter (I2) consists of a NMOS transistor (N2) and a PMOS transistor (P2). The inverters (I1, I2) are subjected to cross section. The NMOS transistor (N1) is formed within a P well region (PW0), and the NMOS transistor (N2) is formed within a P well region (PW1). The P well regions (PW0, PW1) are oppositely disposed with an N well region (NW) interposed therebetween.

Abstract: An LED apparatus includes a base having thermal conductivity, an insulative substrate provided on one surface of the base and including electrodes provided on a surface of the substrate, at least one base-mounting area that is an exposed part of the base, exposed within a pass-through hole provided in the substrate, a plurality of LED elements mounted on the base in the base-mounting area and some of the LED elements in a unit electrically connected to the electrodes in series, a plurality of the units are electrically connected in parallel, and a frame disposed to surround the base-mounting area and configured to form a light-emitting area.

Abstract: A non-volatile storage system includes technology for skipping programming cycles while programming a page (or other unit) of data. While programming a current subset of the page (or other unit) of data, the system will evaluate whether the next subsets of the page (or other unit) of data should be programmed into non-volatile storage elements or skipped. Subsets of the page (or other unit) of data that should not be skipped are programmed into non-volatile storage elements. Some embodiments include transferring the appropriate data to temporary latches/registers, in preparation for programming, concurrently with the evaluation of whether to program or skip the programming.

Abstract: A method is disclosed. The method includes receiving an update package from a wireless service provider that includes information indicating that multiple language versions of an update are included in the update package. Based on the information, the method further specifies an update associated with a language from the update package, and transmits the update associated with the language to a wireless device.

Abstract: A method for using a synchrotron, the method including the steps of: providing a synchrotron designed to accelerate a hadron beam to higher momenta; altering said synchrotron to enable deceleration of hadron beams to lower momenta; and using the synchrotron in said altering step in decelerating a hadron beam to lower momentum.

Abstract: A split bridge circuit for rectifying the alternating current house supply into direct current (D.C.), using hi-polar transistor as rectifying devices. Using specified terminals of the bi-polar transistors results in a high forward voltage drop across the transistors (particularly as compared to the voltage drop across diode rectifiers in the prior art circuits), which reduces ripple significantly and lessens, or even eliminates, the need for a series limiting resistor in the circuit.

Abstract: The present invention addresses the problem of providing illumination in a manner that is energy efficient and intelligent. In particular, the present invention uses distributed processing across a network of illuminators to control the illumination for a given environment. The network controls the illumination level and pattern in response to light, sound, and motion. The network may also be trained according to uploaded software behavior modules, and subsets of the network may be organized into groups for illumination control and maintenance reporting.

Abstract: A memory system may provide for a successful write of a multi-port memory cell (e.g., dual-port 2WR SRAM cell) when it is simultaneously accessed by more than one port. This multi-port memory cell may include at least two independent accesses to the memory cell, where each access may be controlled by an independent wordline signal. Each port may have an independent pair of bitlines. Multiple write circuitry (e.g., double write circuitry) may enable the write driver to drive the input data to more than one pair of bitlines simultaneously.

Abstract: An arrangement wherein a plurality of LED strings are driven with a balanced drive signal, i.e. a drive signal wherein the positive side and negative side are of equal energy over time, is provided. In a preferred embodiment, the drive signal is balanced responsive to a capacitor provided between a switching network and a driving transformer. Balance of current between various LED strings is provided by a balancing transformer.

Abstract: A load control device for controlling the amount of power delivered to an electrical load (e.g., an LED light source) comprises an isolated forward converter comprising a transformer, a controller, and a current sense circuit operable to receive a sense voltage representative of a primary current conducting through to a primary winding of the transformer. The primary winding is coupled in series with a semiconductor switch, while a secondary winding is adapted to be operatively coupled to the load. The forward converter comprises a sense resistor coupled in series with the primary winding for producing the sense voltage that is representative of the primary current. The current sense circuit receives the sense voltage and averages the sense voltage when the semiconductor switch is conductive, so as to generate a load current control signal that is representative of a real component of a load current conducted through the load.

Abstract: The present invention provides LEDs and zener diodes that are homo-polar and connected in parallel to constitute the first set of LED and zener diode and a second set of LED and zener diode; the first LED and zener diode set and the second LED and zener diode assume a reverse polarity series connection to constitute the voltage-limiting and reverse polarity series type LED device; through the selection of connecting pins, it is used on direct current power source or alternating current power source which is its characteristics.

Abstract: A device for generating clock signals for use with a plurality of DDR memory devices on a dual in-line memory module (DIMM) board is provided that has a data buffer for buffering data. A clock divider divides a first clock signal (CLK1) having a first clock frequency to generate a second clock signal (CLK20) having a second clock frequency which is an integer multiple of the first clock frequency. A shift register (SH) receives the second clock signal as a data input signal, and comprises a plurality flip-flops having clock inputs coupled to receive the first clock signal (CLK1), and further coupled so that the data output of a preceding flip-flop is coupled to be the data input of a following flip-flop. The second clock signal is shifted through the shift register (SH) in response to the first clock signal (CLK1) to generate a plurality of shifted clock signals (CLK 21, . . . , CLK32) at respective data outputs of the plurality of flip-flops.

Abstract: An impedance tuner may include a transmission media for propagating RF signals, a reflection magnitude control device mounted in a fixed position relative to a direction of signal propagation along said transmission media, and a phase shifter to control a reflection phase. A multi-section probe for an impedance tuner system may include a plurality of probe sections and a holder structure for mechanically supporting the plurality of probe sections.

Abstract: The present invention generally relates to data acquisition, analysis, and management system for professionals and organizations of all sizes across many different industries. Specifically, the present invention provides systems and methods for tracking, billing, logging, reporting, archiving, searching, and mining on- and off-line user interactions. Not only does the present invention provide methods that simplify business and/or academic research activities, but provides an easy way to build and manage a scalable and secure e-library system. The present invention includes a unique log, report, search, and annotation engines, plus personalization and customization features. Sophisticated data acquisition, analysis, and management modules are hidden behind a simple toolbar embedded in the Network browser on a client computer.

Abstract: A circuit for generating an output voltage to a top node of a plurality of LED strings. The circuit includes an inductor having a load current flowing therethrough and a switching transistor responsive to a switching control signal. An integrator generates a compensation voltage responsive to a voltage at a bottom node of the LED string and a reference voltage. Circuitry for combining an a correction offset with the compensation voltage is responsive to the compensation voltage and the load current through the inductor. The offset is generated only during a step load change of the load current and substantially reduces voltage transients from the compensation voltage and the output voltage. A summation circuit sums the compensation voltage including the correction offset with at least the voltage at the bottom node of the LED string to generate a first control signal. A latch generates the switching control signal responsive to the first control signal and a leading edge blanking signal.

Abstract: In a microstrip antenna in which a ground conductor is provided to be opposed to patch conductors, wedge shapes angled to intersect with an antenna polarization plane are provided at edges of the ground conductor in a repeated manner.

Abstract: An integrated circuit includes a NAND string including a string selection transistor SST and a ground selection transistor GST disposed at either end of series-connected memory storage cells MC. Each of the memory storage cells is a memory transistor having a floating gate, and at least one of the string selection transistor SST and the ground selection transistor GST is a memory transistor having a floating gate. The threshold voltage Vth of programmable string selection transistors SST and the ground selection transistor GST is variable and user controllable and need not be established by implantation during manufacture. Each of the programmable string selection transistors SST and the ground selection transistors GST in a memory block may be used to store random data, thus increasing the memory storage capacity of the flash memory device.