Abstract: A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first conductive line and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first substrate. The first conductive line is over the first shielding layer. The first IMD layer is between the first substrate and the first conductive line.

Abstract: According to one embodiment, a display device includes an insulating substrate, a first transistor including a first semiconductor layer of silicon and a first electrode, a first insulating layer provided above the first semiconductor layer, a second transistor including a second semiconductor layer of an oxide semiconductor, a second electrode and a conductive layer electrically connected to the second semiconductor layer, and a second insulating layer provided above the first insulating layer and the second semiconductor layer, the first electrode being electrically connected to the first semiconductor layer in a first hole, and the second electrode being in contact with the conductive layer in a second hole.

Abstract: An apparatus includes a base portion having an upper surface and a lower surface opposite the upper surface. The apparatus also includes a first sidewall portion having a first upper portion distal the upper surface of the base portion and a first slanted sidewall between the first upper portion and the upper surface of the base portion. The apparatus further includes a second sidewall portion having a second upper portion distal the upper surface of the base portion and a second slanted sidewall between the second upper portion and the upper surface of the base portion. The first sidewall portion and the second sidewall portion define a first reservoir between the first slanted sidewall and the second slanted sidewall, the first reservoir being configured to receive a first chip package portion and to secure the first chip package portion in a first curing position.

Abstract: A semiconductor gas sensor includes a substrate having a cavity, a first insulation layer formed on the substrate, including an exposure hole formed at a position corresponding to the cavity and a peripheral portion of the cavity, a second insulation layer formed on the first insulation layer, covering the exposure hole, a heating electrode formed on the second insulation layer, being formed at a position corresponding to the cavity, a sensing electrode formed over the heating electrode, being electrically insulated from the heating electrode, a detection layer covering the sensing electrode, being capable of having a variable resistance when acting with a predetermined kind of gas, and a vent hole formed by penetrating the second insulation layer to communicate with the exposure hole, and the vent hole being capable of dissipating heat from the heating electrode in a upward direction with respect to the substrate.

Abstract: A semiconductor device and method of fabricating the same are disclosed. The method includes depositing a polysilicon gate layer over a gate dielectric formed over a surface of a substrate in a peripheral region, forming a dielectric layer over the polysilicon gate layer and depositing a height-enhancing (HE) film over the dielectric layer. The HE film, the dielectric layer, the polysilicon gate layer and the gate dielectric are then patterned for a high-voltage Field Effect Transistor (HVFET) gate to be formed in the peripheral region. A high energy implant is performed to form at least one lightly doped region in a source or drain region in the substrate adjacent to the HVFET gate. The HE film is then removed, and a low voltage (LV) logic FET formed on the substrate in the peripheral region. In one embodiment, the LV logic FET is a high-k metal-gate logic FET.

Abstract: A method for fabricating an advanced metal insulator metal capacitor structure includes providing a pattern in a dielectric layer. The pattern includes a set of features in the dielectric layer. A first metal layer is deposited in the set of features in the dielectric layer. A phase change material layer is deposited over the metal layer in the set of features in the dielectric layer. The phase change material is an insulator in a deposited state. A surface treatment process is performed on the phase change layer to produce a top surface layer having electrically conductive properties. A second metal layer is deposited on the top surface layer of the phase change layer.

Abstract: A light emitting device includes a semiconductor chip including a p-type semiconductor layer and an n-type semiconductor layer, the semiconductor chip being adapted to emit light between the p-type semiconductor layer and the n-type semiconductor layer; a p-side pad electrode disposed on an upper surface side of the semiconductor chip and over the p-type semiconductor layer; an n-side pad electrode disposed on an upper surface side of the semiconductor chip and over the n-type semiconductor layer; a resin layer disposed to cover the upper surface of the semiconductor chip; a p-side connection electrode and an n-side connection electrode disposed at an outer surface of the resin layer and positioned on the upper surface side of the semiconductor chip; and a metal wire disposed in the resin. The metal wire is adapted to make connection at least one of between the p-side pad electrode and the p-side connection electrode, and between the n-side pad electrode and the n-side connection electrode.

Abstract: A power integrated device includes a channel region, a source region, a drift region, and a drain region. A stacked gate includes a gate insulation layer and a gate electrode. The stacked gate having a plurality of stacked gate extension portions that extend from the stacked gate to over the plurality of deep trench field insulation layers. A plurality of deep trench field insulation layers is disposed in the drift region. The deep trench field insulation layers are spaced apart from each other in a channel width direction. A height of the deep trench field insulation layers is greater than a width of the deep trench field insulation layer.

Abstract: The present invention relates to a light emitting diode (LED) chip, in which a hybrid sensor is formed in a nitride-based LED structure. A chip structure embedded with such a hybrid sensor functions as an LED light emitting sensor which can monitor environmental pollution while functioning as a lighting element at the same time and has an effect of being used as a variety of environment pollution sensors according to the type of an electrode material.

Abstract: An array substrate including a substrate, a plurality of gate lines and a plurality of data lines disposed on the substrate, which intersect to define a plurality of pixel units, a common electrode including a planar shape disposed above the pixel units, a plurality of strip slits are disposed within a region of the common electrode that corresponds to the pixel units, major axes of a plurality of the strip slits corresponding to the same row of pixel units are parallel to each other, extension lines of the major axes of the strip slits corresponding to a row of the pixel units intersect extension lines of the major axes of the strip slits corresponding to an adjacent row of the pixel units; wherein, a first angle is defined between the major axis of one of the strip slits and a direction perpendicular to the gate lines.

Abstract: Provided is a semiconductor device including a substrate with an active pattern, a gate electrode crossing the active pattern, a source/drain region in an upper portion of the active pattern at a side of the gate electrode, the source/drain region including a recess region at an upper region thereof, a contact electrically connected to the source/drain region, the contact including a lower portion provided in the recess region, and a metal silicide layer provided at a lower region of the recess region and between the source/drain region and the contact.

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

Abstract: Methods and materials for making a semiconductor device are described. The method includes forming a surface preparation layer over the semiconductor substrate. The surface preparation material layer includes an aziridine structure. A coating layer may then be deposited on the surface preparation material layer.

Abstract: An LTPS array substrate and a method for producing the same are proposed. The method includes: forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one; exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer; forming a source and a drain of the TFT on the polycrystalline silicon layer; forming a pixel electrode on the insulating layer and part of the source; forming a plain passivation layer on a source-drain electrode layer; forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is connected to the gate, the source, and the drain via the contact hole. The use of masks in types and numbers in the LTPS technology can be reduced. Thus, both of the processes and the production costs are reduced.

Abstract: A thin-film transistor array substrate for AMOLED and a manufacturing method thereof are disclosed. The thin-film transistor array substrate includes: a substrate; a plurality of thin-film transistor pixel units mounted on the substrate, each of which includes at least one driving thin-film transistor and at least one switching thin-film transistor; a first electrode pattern layer mounted on the substrate; an insulating layer mounted on the substrate and covering gates of the driving thin-film transistor and the switching thin-film transistor and the first electrode pattern layer; and a second electrode pattern layer mounted on the insulating layer and partially overlapped with the first electrode pattern layer to have an overlapping area and a non-overlapping area; the insulating layer has a larger thickness in the overlapping area and has a smaller thickness in the non-overlapping area.

Abstract: An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin, the second doped region includes a second portion of the substrate, a second region of the first fin adjacent to the first region and the second fin. The ESD device also includes a first gate structure on a surface portion of the first region and a surface portion of the second region of the first fin and including, from bottom to top, an interface layer on the surface portion of the first region and the surface portion of the second region of the first fin, a spacer, a high-k dielectric layer, a first work-function adjusting layer, a second work-function adjusting layer, and a gate.

Abstract: A method forms a vertical output coupler for a waveguide, formed of waveguide material and disposed within a layer stack on a top surface of a wafer. The method includes etching through a portion of the wafer to form a via that exposes the waveguide material, and etching the waveguide material to remove at least a first portion of the waveguide. The etching forms a tilted plane in the waveguide material. The method further includes coating the first tilted plane with one or more reflective layers, to form a tilted mirror in contact with the first tilted plane in the waveguide material. The tilted mirror forms the vertical output coupler such that light propagating through the waveguide is deflected by the tilted mirror, and exits the waveguide.

Abstract: A MISFET is formed to include: a co-doped layer that is formed over a substrate and has an n-type semiconductor region and a p-type semiconductor region; and a gate electrode formed over the co-doped layer via a gate insulation film. The co-doped layer contains a larger amount of Mg, a p-type impurity, than that of Si, an n-type impurity. Accordingly, the carriers (electrons) resulting from the n-type impurities (herein, Si) in the co-doped layer are canceled by the carriers (holes) resulting from p-type impurities (herein, Mg), thereby allowing the co-doped layer to serve as the p-type semiconductor region. Mg can be inactivated by introducing hydrogen into, of the co-doped layer, a region where the n-type semiconductor region is to be formed, thereby allowing the region to serve as the n-type semiconductor region. By thus introducing hydrogen into the co-doped layer, the p-type semiconductor region and the n-type semiconductor region can be formed in the same layer.

Abstract: A light-emitting device that may be manufactured includes an n-type semiconductor layer including a first dopant on a substrate, an active layer on the n-type semiconductor layer, and a p-type semiconductor layer including a second dopant on the active layer. The light-emitting device may be formed according to at least one of a first layering process and a second layering process. The first layering process may include implanting the first dopant into the n-type semiconductor layer into the n-type semiconductor layer according to an ion-implantation process, and the second layering process may include implanting the second dopant into the p-type semiconductor layer according to an ion-implantation process. Forming a semiconductor layer that includes an ion-implanted dopant may include thermally annealing the semiconductor layer subsequent to the ion implantation.

Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.