Patents Examined by April Y Blair
  • Patent number: 10353598
    Abstract: Systems, apparatuses, and methods are provided that refresh data in a memory. Data is programmed into the memory. After which, part or all of the data may be refreshed. The refresh of the data may be different from the initial programming of the data in one or more respects. For example, the refresh of the data may include fewer steps than the programming of the data and may be performed without erasing a section of memory. Further, the refresh of the data may be triggered in one of several ways. For example, after programming the data, the data may be analyzed for errors. Based on the number of errors found, the data may be refreshed.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: July 16, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Jianmin Huang, Bo Lei, Jun Wan, Niles Yang
  • Patent number: 10353771
    Abstract: There are disclosed computer-implemented methods, apparatus, and computer program products for managing data storage. In one embodiment, the computer-implemented method comprises the step of receiving new data to be written to storage. The method also comprises the step determining that the new data does not form a full stripe of data. The method also comprises reading missing non-parity data in the stripe of data. The method further comprises determining new parity based on the new data and the missing non-parity data. The method still further comprises writing the new data and the new parity to storage in a manner that does not require the missing non-parity data to be written to storage.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: July 16, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Marc C. Cassano, Robert P. Foley, Daniel E. Cummins, Socheavy D Heng
  • Patent number: 10355714
    Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver is formed of a plurality of columns each including a plurality of rows and includes a block interleaver configured to divide each of the plurality of columns into a first part and a second part and interleave the LDPC codeword, the number of rows constituting each column divided into the first part is determined differently depending upon the modulation method, wherein the number of rows constituting each column divided into the second part is determined depending upon the number of rows constituting each column divided into the first part.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 10354742
    Abstract: An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: July 16, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Swapnil Bahl, Shray Khullar
  • Patent number: 10353000
    Abstract: A multi-bit flip-flop includes: a single scan input pin to receive a scan input signal, a plurality of data input pins to receive first and second data input signals, a first scan flip-flop to select one of the scan input signal and the first data input signal as a first selection signal in response to a scan enable signal and to latch the first selection signal to provide a first output signal, a second scan flip-flop to select one of an internal signal corresponding to the first output signal and the second data input signal as a second selection signal in response to the scan enable signal and to latch the second selection signal to provide a second output signal, and a plurality of output pins to output the first and second output signals, wherein scan paths of the first and second scan flip-flops are connected to each other.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: July 16, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Doo-Seok Yoon, Min-Su Kim, Chung-Hee Kim, Dae-Seong Lee, Hyun Lee, Matthew Berzins, James Lim
  • Patent number: 10338136
    Abstract: An integrated circuit operable in a scan mode includes a scan chain formed by cascaded flip-flop cells. Each flip-flop cell includes a master latch that receives a first data signal and generates a first latch signal, a slave latch that receives the first latch signal and generates a second latch signal, and a multiplexer having first and second inputs respectively connected to the master and slave latches that receives a first input signal and the second latch signal, and generates a scan data output signal depending on an input trigger signal. The first input signal is one of the first data signal and the first latch signal. The clock signal provided to the slave latch is gated by the input trigger signal.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: July 2, 2019
    Assignee: NXP USA, INC.
    Inventors: Ling Wang, Wanggen Zhang, Wei Zhang
  • Patent number: 10340948
    Abstract: A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 2, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenya Sugihara, Yoshikuni Miyata, Wataru Matsumoto
  • Patent number: 10340952
    Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: July 2, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong
  • Patent number: 10331515
    Abstract: A computing system includes: a data block including data pages and each of the data pages includes data sectors and each of the data sectors include sector data and a sector redundancy; a storage engine, coupled to the data block, configured to: apply a first protection across the data pages includes shifted parities generated, apply a second protection across the data sectors, and correct at least one of the data sectors when a sector correction with the sector redundancy failed by selecting one of the shifted parities for the first protection and the second protection.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: June 25, 2019
    Assignee: CNEX LABS, Inc.
    Inventors: Alan Armstrong, Patrick Lee
  • Patent number: 10333555
    Abstract: An example methods for interleaved BCH codes can include encoding a plurality of portions of data using a first generator polynomial to obtain a plurality of respective BCH codewords. The method can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The method can include outputting the plurality of respective BCH codewords and the additional BCH codeword.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Yingquan Wu
  • Patent number: 10332613
    Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for assuring retention are disclosed. The nonvolatile memory controller includes a retention monitor that stores test characteristics corresponding to a use case and determines, each time that a read of a codeword is performed, whether the number of errors in the codeword exceed a retention threshold. If the number of errors in the codeword exceed the retention threshold, the block containing the codeword is retired. The retention monitor performs retention tests during the operation of the memory controller and adjusts the retention threshold when the results of the retention tests indicate deviation from the test characteristics corresponding to a use case.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: June 25, 2019
    Assignee: Microsemi Solutions (US), Inc.
    Inventors: Rino Micheloni, Alessia Marelli, Robert Scott Fryman
  • Patent number: 10330727
    Abstract: A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: June 25, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Nuo Xu, Jing Wang, Woosung Choi
  • Patent number: 10324130
    Abstract: A test decompressor and a test method thereof for converting original input data of one single test input into test vectors for testing a circuit under test (CUT) containing scan chains are revealed. The test decompressor includes a test data spreader, a test configuration switch, and a test controller. The test data spreader converts the original input data into a plurality of test data. The test configuration switch receives the original input data and the plurality of test data and transfers these data to scan chains of the CUT. The test controller receives the original input data and outputs a select signal to the test configuration switch for switching current test configuration to another test configuration. The scan chains in the CUT are divided into several scan groups and the scan chains in each scan group share the same test data. Thus the test data volume can be significantly reduced.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 18, 2019
    Assignee: National Cheng Kung University
    Inventors: Kuen-Jong Lee, Jhen-Zong Chen
  • Patent number: 10324790
    Abstract: A logical storage layer for shared storage systems interposes between address ranges of the shards and the storage devices on which the shards are stored. The shards may be logically addressed using a plurality of addressable zones, to which the storage devices are independently mapped. Data requests related to a given piece of data associated with a shard may involve multiple storage devices, and vice versa.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: June 18, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Paul David Franklin, Bryan James Donlan, Colin Laird Lazier
  • Patent number: 10324129
    Abstract: An integrated circuit (IC) automatic test system and an IC automatic test method storing test data in scan chains are revealed. The automatic test system includes at least one scan chain, a test controller and a test decompressor connected. Each scan chain consists of a storage portion with a plurality of scan units and a scan input corrector. The storage portion is for storing test data and the scan input corrector is used to adjust test patterns to be shifted into the scan chains. The test controller is for control of test flow while the test decompressor reconstructs and decompresses the test data stored in the storage portions of the scan chains to generate test patterns for the circuit under test. Thereby the IC electrical test is performed automatically and the test cost and the test cost is reduced.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 18, 2019
    Assignee: National Cheng Kung University
    Inventors: Kuen-Jong Lee, Ping-Hao Tang
  • Patent number: 10319457
    Abstract: Embodiments include methods, and computer system, and computer program products for testing directly and indirectly anchored interfaces for vulnerabilities regarding storage protection keys.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bryan C. Childs, Karl D. Schmitz
  • Patent number: 10318389
    Abstract: Methods and apparatus deduplicate and erasure code a message in a data storage system. One example apparatus includes a first chunking circuit that generates a set of data chunks from a message, an outer precoding circuit that generates a set of precoded data chunks and a set of parity symbols from the set of data chunks, a second chunking circuit that generates a set of chunked parity symbols from the set of parity symbols, a deduplication circuit that generates a set of deduplicated data chunks by deduplicating the set of precoded chunks or the set of chunked parity symbols, an unequal error protection (UEP) circuit that generates an encoded message from the set of deduplicated data chunks, and a storage circuit that controls the data storage system to store the set of deduplicated data chunks, the set of parity symbols, or the encoded message.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 11, 2019
    Assignee: Quantum Corporation
    Inventors: Suayb S. Arslan, Turguy Goker, Roderick B. Wideman
  • Patent number: 10320420
    Abstract: Bit-flip coding uses a bit-flip encoder to flip bits in a redundancy-intersecting vector of a binary array having n rows and n columns until Hamming weights of the binary array are within a predetermined range ? of n divided by two. Information bits of an input data word to the bit-flip coding apparatus are stored in locations within the binary array that are not occupied by n redundancy bits of a redundancy vector.
    Type: Grant
    Filed: January 24, 2014
    Date of Patent: June 11, 2019
    Assignee: Hewlett-Packard Enterprise Development LP
    Inventors: Erik Ordentlich, Ron M. Roth
  • Patent number: 10318378
    Abstract: The present disclosure includes a redundant array of independent NAND for a three dimensional memory array. A number of embodiments include a three-dimensional array of memory cells, wherein the array includes a plurality of pages of memory cells, a number of the plurality of pages include a parity portion of a redundant array of independent NAND (RAIN) stripe, and the parity portion of the RAIN stripe in each respective page comprises only a portion of that respective page.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc
    Inventors: Jung Sheng Hoei, Sampath K. Ratnam, Renato C. Padilla, Kishore K. Muchherla, Sivagnanam Parthasarathy, Peter Feeley
  • Patent number: 10320520
    Abstract: Provided is a method for effectively suppressing packet losses by burst losses without an increase in delay by adaptively or fixedly changing a size of an FEC encoded block even when the number of packets per unit time is small. Each communication device 101 includes a transmitting unit 102 and a receiving unit 103. The transmitting unit 102 has a function of calculating forward error correction (FEC) codes based on the number of packets per encoding time and a value of a burst loss time of a network line. The receiving unit 103 decodes an FEC encoded packet and measures line quality information of the network for transmission to the transmitting unit 102. The transmitting unit 102 transmits the packets at equal intervals for as long as it is required for encoding, and can change a system for calculating FEC based on the burst loss time and the encoding time.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: June 11, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Takeuchi, Ryosuke Fujiwara