Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder which encodes input bits including outer encoded bits to generate an LDPC codeword including the input bits and parity bits to be transmitted to a receiver in a current frame; a puncturer which punctures a part of the parity bits which is not transmitted in the current frame; and an additional parity generator which selects at least a part of the parity bits to generate additional parity bits transmitted to the receiver in a previous frame of the current frame, wherein a number of the additional parity bits is determined based on a number of the outer encoded bits and a number of the parity bits left after the puncturing.

Abstract: Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A transmitting apparatus and a receiving apparatus are provided. The transmitting apparatus includes: an encoder configured to generate a low density parity check (LDPC) codeword by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to modulate the interleaved LDPC codeword according to a modulation method to generate a modulation symbol. The interleaver includes a block interleaver formed of a plurality of columns each comprising a plurality of rows, and the block interleaver is configured to divide the plurality of columns into at least two parts and interleave the LDPC codeword.

Abstract: A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.

Abstract: Methods, systems, and devices for selectable error control for memory device are described. An apparatus may include a memory array and a circuit configurable to perform a first error control operation and a second error control operation on data stored by the memory array. The circuit may include a first plurality of gates enabled during the first error control operation and configured to generate a first set of bits associated with a first matrix of the first error control operation. The circuit may also include a second plurality of gates enabled during the second error control operation and configured to generate a second set of bits associated with the second matrix of the second error control operation. The circuit may further include a third plurality of gates configured to generate a third set of bits that are common to both the first matrix and the second matrix.

Abstract: An I/O sensor including: a programmable delay line; a delayed clocked receiver having the following inputs: (a) a data signal and a reference voltage that also serve as inputs to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed clocked receiver and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.

Abstract: A method of recovering data from one or more failed data sectors includes estimating a reader offset position from a first or a second read attempt of the one or more failed data sectors at a current set of channel parameters and basing the estimated reader offset position on, at least in part, a position error signal generated during the first or second read attempt. At least one read is performed on the one or more failed data sectors at the estimated reader offset position to obtain one or more samples. The one or more samples are processed to obtain a processed sample. Iterative outer code recovery is performed on the processed sample.

Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.

Abstract: Aspects of the disclosure provide a method and device performing input bit allocation that includes receiving broadcasting information bits, generating timing related bits for the broadcasting information bits, and selecting a portion of the generated timing related bits. The method and device can further include allocating each of the selected timing related bits to selected input bits of an encoder, so that each of the selected timing related bits is allocated to an input bit of the encoder corresponding to an available bit channel of the encoder where the selected inputs bits of the encoder correspond to encoded bits that are located in a front portion of the encoded bits.

Abstract: IHSs (Information Handling Systems) may include connectors, such as an XDP connector, that support couplings by diagnostic tools that utilize a debugging interface that is supported by the IHS, such as JTAG interface. These connectors provide a useful debugging mechanism but may be exploited to access protected information and to install malicious software. Detecting when these debugging capabilities have been compromised is very difficult. In embodiments, a remote access controller of the IHS disables the JTAG interface prior to initialization of the IHS processor by maintaining the interface in reset state. The remote access controller does not include instructions necessary for releasing the JTAG interface from this reset state until its firmware has been updated. If the remote access controller detects debugging activity while the JTAG interface is still in a reset state, the remote access controller signals an attempt to conduct an unauthorized debug session.

Abstract: Systems, apparatuses, and methods related to modified parity data using a poison data unit. An example method can include receiving, from a controller of a memory device, a first set of bits including data and a second set of at least one bit indicating whether the first set of bits comprises one or more erroneous or corrupted bits. The method can further include generating, at an encoder of the memory device, parity data associated with the first set of bits. The method can further include generating, at logic of the memory device, modified parity data with the parity data component and the second set of at least one bit. The method can further include writing the first set of bits and the modified parity data in an array of the memory device.

Abstract: A base station maps code blocks of a transport block of a transport block size (TBS) for a channel using tone-level interleaving or resource element (RE)-level interleaving. Then, the base station can transmit the code blocks of the transport block of the TBS for the channel. A UE may receive the channel from the base station and de-interleave the received tones of the channel in a frequency domain to obtain the code blocks of the transport block having the TBS for the channel.

Abstract: A variety of applications can include systems and methods that include a memory system tester having an analyzer coupled to a test flow controller. The test flow controller can be arranged to generate test signals to a memory system with the analyzer arranged to couple to test pads of a package platform for the memory system. The analyzer can provide data to the test flow controller to conduct testing and/or debugging of the memory system, with the data based on real time monitoring of the test pads of the package platform. In various embodiments, the analyzer can provide data feedback to the test flow controller in real time such that the test flow controller can control the flow of test signals to the memory system in real time. Additional apparatus, systems, and methods are disclosed.

Abstract: A system comprises a plurality of memory devices storing a set of codewords and a processing device, operatively coupled to the plurality of memory devices, to perform operations including: detecting a power-on of the system; determining a read-retry trigger rate (TR) based on reading a subset of the codewords during a time interval directly after actual initialization of the plurality of memory devices, wherein the time interval includes a time period before entering a normal operating mode, and no full-memory refresh operation is performed during the normal operating mode; determining whether the TR satisfies a threshold criterion; and in response to the TR not satisfying the threshold criterion, initializing the full-memory refresh operation of the plurality of memory devices.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.

Abstract: The present disclosure relates to a memory device comprising: an array of memory cells; a plurality of boundary cells able to manage serial and parallel data; mixed pads connected to the memory cells through low speed paths, the mixed pads being configured to be contacted by probes of a testing machine; high speed pads connected to the boundary cells through high speed paths; a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive thereto at least a first input signal and a second input signal, the three state multiplexer block being also connected to the mixed pads; ESD networks connected to the mixed pads; an enabling circuit connected to one of the mixed pads, configured to receive an external enabling signal and to provide the three state MUX with an internal enabling signal; wherein the enabling circuit comprises: a tester presence detector circuit connected to the mixed pad; and a logical gate having respective input terminals connected to t

Abstract: A method of generating an error correction circuit for correcting an error in a codeword read from a memory includes: constructing a generation matrix; transforming the generating matrix into a systematic form, wherein the transformed generating matrix is composed of a parity matrix and a check matrix; sorting rows of the parity matrix according to row weights; determining a number of rows in the parity matrix to be truncated; generating a truncated parity matrix by keeping the sorted rows of the P matrix that have weights less than or equal to weights of the truncated rows of the P matrix so as to minimize a number of logic gate operations; and forming an error correction circuit with the number of logic gate operations minimized according to the truncated P matrix to correct the error of the codeword.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.