Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

Abstract: Methods, systems, and devices for testing of multi-level signaling associated with a memory device are described. A tester may be used to test one or more operations of a memory device. The memory device may be configured to communicate data using a modulation scheme that includes three or more symbols. The tester may be configured to communicate data using a modulation scheme that includes three or fewer symbols. Techniques for testing the memory device using such a tester are described.

Abstract: A transmitter and receiver are provided for communication over a noisy channel in a wireless communications system. The transmitter and receiver use polar coding to provide reliability of data transmission over the noisy wireless channel. In addition, signature bits are inserted in some unreliable bit positions of the polar code. For a given codeword, the receiver with knowledge of the signature can more effectively decode the codeword. Cyclic redundancy check (CRC) bits may also included in the input vector to assist in decoding.

Abstract: Techniques test a storage system. Such techniques involve: acquiring a result of performing a first test on the storage system using a test case; if the result indicates that the storage system fails the first test, performing a second test on the storage system based on a problem of the storage system; and if the result indicates that the storage system passes the first test, determining a security level of the test case based on the result. Such techniques can effectively enhance test performance and system reliability of the storage system.

Abstract: An example memory device includes an array of memory cells, a plurality of boundary cells, mixed pads connected to the memory cells, high speed pads connected to the boundary cells, a three state multiplexer block connected to the memory cells and to the boundary cells and configured to receive at least first and second input signals, and the three state multiplexer block is connected to the mixed pads. The example memory device further includes an enabling circuit connected to a mixed pad and configured to receive an external enabling signal and provide the three state MUX with an internal enabling signal, and comprising: a tester presence detector circuit connected to the mixed pad and configured to provide a presence signal to a logical gate, the logical gate having input terminals connected to the tester presence detector circuit and configured to provide the internal enabling signal.

Abstract: A semiconductor device includes a selection input circuit and a core data generation circuit. The selection input circuit is configured to generate selection data, a selection parity, and a selection data control signal from data, a parity, and a data control signal during a write operation and sets the selection data, the selection parity, and the selection data control signal to a predetermined logic level during a pattern write operation. The core data generation circuit is configured to receive drive data, a drive parity, and a drive data control signal driven by the selection data, the selection parity, and the selection data control signal to generate core data which are stored into a memory core according to whether an error correction operation and a data inversion operation is performed.

Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.

Abstract: An apparatus and method for detecting leakage current in a non-volatile memory array. A reference current is connected to a leakage detection circuit. A reference code is determined for the leakage detection circuit coupled to a switching circuit. The reference code establishes a leakage current threshold. The reference current is disconnected from the leakage detection circuit and the switching circuit. Next, the leakage detection circuit is connected to a set of word lines of a storage block of a non-volatile memory array by way of the switching circuit. A memory current is generated within the set of word lines. A leakage code is determined for the set of word lines representing leakage current from the word lines in response to the memory current. The leakage code is compared with the reference code. If the leakage code exceeds the reference code, the storage block is deemed unusable.

Abstract: A memory device test circuit and a memory device test method are provided. The memory device test circuit is configured to test a memory device and includes a storage circuit, a comparison circuit and a control circuit. The storage circuit stores a test data. The comparison circuit is coupled to the storage circuit. The control circuit is coupled to the storage circuit, the comparison circuit, and the memory device and performs the following steps to test the memory device: writing the test data to the memory device; controlling the memory device to enter a power mode; controlling the memory device to enter a function mode; and controlling the comparison circuit to compare an output data of the memory device with the test data.

Abstract: A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices.

Abstract: A method for identifying outlier devices during testing, includes: establishing binning limits for a device being tested based on one or more rules generated from external test results data of tests involving similar devices; receiving test results data in real time for the device being tested while the device is on a device tester; applying the one or more rules to the test results data for the device in real time; determining in real time, based on results of applying the one or more rules to the test results data, whether the device is an outlier with respect to the binning limits; and in response to determining that the device is an outlier, binning the outlier device separately from tested devices having test results data falling within the binning limits.

Abstract: Provided are a Cyclic Redundancy Check (CRC) circuit, and a method and an apparatus thereof, a chip and an electronic device, which belong to the technical field of computers. Herein, the cyclic redundancy check circuit may include: a configuration module configured to acquire configuration information and an information field, a CRC arbitration module configured to determine a generator polynomial according to the configuration information, a CRC control module configured to respond to triggering of the CRC arbitration module and output a clock signal, a coefficient corresponding to each power in the generator polynomial and the information field, a parallel iteration module configured to respond to the clock signal and implement parallel iteration for the information field according to the coefficient corresponding to the each power in the generator polynomial, as to output an iteration result, and a CRC output module configured to package the information field according to the iteration result.

Abstract: According to certain embodiments, a method for use in a transmitter comprises selecting an information set or sequence of information sets for polar encoding. The information set or sequence of information sets are selected from a plurality of information sets based on one or more system parameters and/or one or more link measurements. The method further comprises performing polar encoding for a plurality of data bits to yield encoded data. The polar encoding is performed according to the selected information set or sequence of information sets. The method further comprises transmitting the encoded data to a receiver.

Abstract: Various embodiments disclosed herein provide for a transmission system using codeblock segmentation that does not have to retransmit each of the codeblock segments if one of the codeblock segments is determined to have an error at the receiver. The transmitter segments a transport block into a group of codeblock segments, each having respective cyclic redundancy check bits. The receiver receives the group of codeblock segments, and during decoding, if it is determined that one of the segments have an error, instead of just sending back to the transmitter a negative acknowledgement (NAK) the receiver can send back a NAK as well as an indicator of which segment was in error. The transmitter can then resend just the segment in error in order to improve efficiency and decrease power requirements.

Abstract: A first serializing stage is provided with a stream of data words composed of sub-words that each have values that associate each of the sub-words with the same error detection code value. For example, the values selected for each sub-word may each be associated with even parity. One or more serializing stages time-multiplex the sub-words into a stream of sub-word sized data. At the serializing stage that receives sub-word sized data stream, the data is checked to determine whether any of the sub-words is no longer associated with the error detection code value. Serializing/deserializing stages are selectively controlled to replace one or more data bits from a word being serialized/deserialized with an error detecting code value (e.g., parity). A subsequent serializing/deserializing stage is enabled to use the inserted error detecting code values and the data in the received words to determine whether an error has occurred.

Abstract: A method and apparatus for masking errors in a DRAM write are disclosed to perform a partial write request with an SSD controller. In embodiments, write data from a host is provided to the controller that is not aligned to the DRAM data. The controller issues a read command from the LBA of a data storage device, and a corresponding write command to write the data received from the host, prior to receipt of the read data, to perform a partial write. The read data is error corrected, and in the event an error is found in the read data, bytes containing an error are masked. The read data, including masked read data, and write data are merged to form partial write data, and written to the DRAM. In certain embodiments, the partial write data may be provided to a logic analyzer to assess the masked read data for debug analysis.

Abstract: A reception apparatus includes a receiver and circuitry. The receiver receives, from a transmission apparatus, a plurality of packets that include code word symbols which include an information word symbol and a parity symbol. The information word symbol is generated from transmission information. The parity symbol is calculated from the information word symbols. The circuitry decodes the code word symbols that are included in the plurality of packets. The number of first packets and the number of second packets among the plurality of packets are shared between the transmission apparatus and the reception apparatus. Each of the first packets includes the information word symbol. Each of the second packets includes the parity symbol.

Abstract: A semiconductor device comprises a data region including a plurality of first semiconductor chips and configured to store data requested by a host, and a metadata region including one or more second semiconductor chips and configured to store metadata corresponding to the plurality of first semiconductor chips in the data region. The data region and the metadata region are accessed using different signals to perform a command-based operation corresponding to a command signal.

Abstract: This invention presents a method and apparatus for vertical layered finite alphabet iterative decoding of low-density parity-check codes (LDPC) which operate on parity check matrices that consist of blocks of sub-matrices. The iterative decoding involves passing messages between variable nodes and check nodes of the Tanner graph that associated with one or more sub-matrices constitute decoding blocks, and the messages belong to a finite alphabet. Various embodiments for the method and apparatus of the invention are presented that can achieve very high throughputs with low hardware resource usage and power.

Abstract: A method of hierarchical structuring a multi-level memory in a convolutional neural network, includes partitioning a memory into a plurality of sections, partitioning the plurality of sections into a plurality of stripes, utilizing input data from the plurality of stripes in a MAC array, outputting an intermediate result from the MAC array to at least one of the plurality of stripes of a result buffer, looping back the intermediate result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an input data buffer and outputting a final result from the at least one of the plurality of stripes of the result buffer to at least one of the plurality of stripes of an output buffer.