Abstract: A computing system is disclosed. The computing system includes a computation unit, one or more processors, a volatile memory, and a non-volatile memory communicatively coupled to the one or more processors and having instructions stored thereon, which when executed by the one or more processors, causing the one or more processor to instantiate a container and perform at least one of a volatile memory checking procedure or a non-volatile memory checking procedure. The volatile memory checking procedure includes checking the first physical address space for errors, loading a container into volatile memory containing the first physical address space if an error is determined, rechecking the first physical address space for error, loading the container to a second physical address space and updating a memory management unit if an error in the first physical address space is determined.

Abstract: Embodiments of the application provides a method for encoding. The method includes: receiving a to-be-encoded data block; encoding the data block at an aggregation level of 2L, where a formula used during the encoding is as follows: [ u . 2 ? ? L u . L ] ? [ G LN 0 G LN G LN ] = ? C . 2 ? ? L C . L ? ( I ) u . L = { u L u L - 1 … u 1 } , u . 2 ? ? L = ? { u 2 ? L u 2 ? L - 1 … u L + 1 } , ? c . L = { c L c L - 1 … c 1 } , c . 2 ? ? L = { c 2 ? L c 2 ? L - 1 … c L + 1 } , G LN = G N ? log 2 ( L ) ( II ) L=2n, and n is a natural number greater than or equal to 0; and outputting an encoded data block.

Abstract: The application provides a channel encoding method, an encoding apparatus, and a system. A bit sequence X1N is output by using X1N=D1NFN, where D1N is a bit sequence obtained after an input bit sequence u1N is encoded based on locations of K to-be-encoded information bits in an encoding diagram that has a mother code length of N, u1N is a bit sequence obtained based on the K to-be-encoded information bits, and FN is a Kronecker product of log2 N matrices F2. A design considers that the locations of the K to-be-encoded information bits in the encoding diagram that has a mother code length of N include a row location index set H of the information bits in the encoding diagram and a layer location index set M of the information bits in the encoding diagram, where 0?H?N, and 0<M?logm N?1.

Abstract: Provided is a coding unit to determine the number of code block groups, divide an input bit sequence to code block segmentation into code block groups of the number of the code block groups, determine the number of code blocks for each of the code block groups, divide each of the code block groups into code blocks of the number of the code blocks, and apply channel coding to each of the code blocks.

Abstract: An error protection key generation method and system are provided, the method being used to generate a key for use in computing an error protection code for an input data value according to a chosen error protection scheme. The method comprises inputting a plurality of desired data value sizes, and then applying a key generation algorithm to generate a key for use in computing the error protection code for a maximum data value size amongst the plurality of data value sizes. The key generation algorithm is arranged so that it generates the key so as to comprise a plurality of sub-keys, where each sub-key is associated with one of the input data value sizes, and where each sub-key conforms to a key requirement of the error protection scheme. As a result, a generic key is produced containing a plurality of sub-keys, where each sub-key is associated with a particular desired data value size, and can be extracted and used independently given that each sub-key conforms to the error protection scheme requirements.

Abstract: A sensor system is configured to communicate at least partially protected sensor data over a communication interface. The sensor system includes a sensor element and a communication interface communicatively coupled to the sensor element. The sensor element is configured to provide sensor data in the digital domain. The communication interface is configured to generate a data package for transmission over the communication interface from the sensor data. The data package includes a data grouping comprising one or more nibbles related to the sensor data. The data package further includes a nibble indicia based on at least a portion of selected nibbles within the data grouping.

Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 5/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Abstract: Memory controllers, decoders and methods to selectively perform bit-flipping (BF) decoding and min-sum (MS) decoding on codewords of an irregular low-density parity-check (LDPC) code. Bit-flipping (BF) decoding is executed with respect to variable nodes having relatively high column weights. MS decoding is executed with respect to variable nodes having relatively low column weights. A column-weight threshold is used to group the variable nodes into the higher and lower column weight groups. The two decoding techniques exchange results during the overall decoding process.

Abstract: A method in a node (110, 115) comprises generating (604) a plurality of constituent polar codes, each of the plurality of constituent polar codes having an associated block length and an associated set of information bits. The method comprises coupling (608) at least a portion of the sets of information bits associated with each of the plurality of constituent polar codes to generate a spatially coupled polar code. The method comprises encoding (612) a wireless transmission using the spatially coupled polar code.

Abstract: A method comprising: identifying, by a resource manager, a resource of a storage system, the resource being one which a testing system lacks permission to use for testing the storage system; adding, by the resource manager, the resource to a group of resources which the testing system is permitted to use for testing the storage system, wherein adding the resource to the group includes granting the testing system a temporary permission to use the resource for testing the storage system; allocating the resource to a test that is performed by the testing system; and removing, by the resource manager, the resource from the group wherein removing the resource from the group includes revoking the temporary permission.

Abstract: Boundary test circuit, memory and boundary test method are provided. The boundary test circuit may include a plurality of serially-connected wrapper boundary registers (WBRs) and a plurality of toggle circuits (TCs). Each WBR may include a first I/O for receiving an initial test signal and a second I/O for transmitting the initial test signal to the WBR at a succeeding stage. Each TC may include an input for receiving the initial test signal stored in a corresponding WBR, a control I/O for receiving a toggle signal, and an output for transmitting a real-time test signal to the integrated circuit. The toggle signal may be configured to control phase switching of the real-time test signal, and, depending on the toggle signal, the real-time test signal may have a phase identical or inverse to a phase of the initial test signal. This method improves the efficiency and flexibility of the boundary test.

Abstract: A method for determining the n best positions of frozen bits in a channel decoder for a noisy communication channel. A decoding method and decoding processing unit for implementing the channel having frozen bits at the n worst positions. A method and system that iteratively, for each bit i from the n bits, determines a probability vector for the bit i by traversing a logical graph using contraction identities simplified to specific values, indexes the specific values from the contraction identities newly computed during the determination of the probability vector for subsequent reference during a following iteration based on corresponding contraction identities, fixes the bit i from the probability vector and moving to bit i+1 until all n bits are fixed.

Abstract: A data storage device and a method for sharing memory of controller thereof are provided. The data storage device comprises a non-volatile memory and a controller, which is electrically coupled to the non-volatile memory and comprises an access interface, a redundant array of independent disks (RAID) error correcting code (ECC) engine and a central processing unit (CPU). The CPU has a first memory for storing temporary data, the RAID ECC engine has a second memory, and the controller maps the unused memory space of the second memory to the first memory to be virtualized as part of the first memory when the second memory is not fully used so that the CPU can also use the unused memory space of the second memory to store the temporary data.

Abstract: The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.

Abstract: An access device includes a memory controller coupled to a memory device and configured to access the memory device. The memory controller is further configured to perform a test procedure on the memory device to obtain a test result, write a boot code index, which indicates a predetermined address for storing predetermined system data of the memory device and a copy rule adopted for generating one or more duplicates of the predetermined system data, in the memory device, establish system data of the memory device according to the test result, write the system data into the predetermined address as the predetermined system data, and write the system data in one or more memory blocks of the memory device as the duplicates of the predetermined system data according to the copy rule.

Abstract: One embodiment of the present disclosure describes a memory system that may include one or more memory devices that may store data. The memory devices may receive command signals to access the stored data as a loopback signal. The memory devices may operate in a normal operational mode, a loopback operational mode, a retrieval operational mode, a non-inverting pass-through operational sub-mode, and an inverting pass-through operational sub-mode. The operational modes facilitate the transmission of the loopback signal for the purpose of monitoring of memory device operations. A selective inversion technique, which uses the operational modes, may protect the loopback signal integrity during transmission.

Abstract: A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode outer-encoded bits to generate an LDPC codeword including LDPC information bits and parity bits; a puncturer configured to puncture some of the parity bits included in the LDPC codeword; and a mapper configured to map the LDPC codeword except the punctured parity bits to symbols for transmission to a receiver, wherein the puncturer calculates a number of parity bits to be punctured among the parity bits included in the LDPC codeword based on a number of the outer-encoded bits, a number of the LDPC information bits, and a minimum number of parity bits to be punctured among the parity bits included in the LDPC codeword.

Abstract: An integrated circuit having a secure domain is disclosed. Circuitry within the integrated circuit is used to select one of a plurality of scan modes. The sequence used to select one of the scan modes also serves to reset all of the flip-flops in the secure domain. In this way, it is impossible for a hacker to use the test modes to shift data from the secure domain out of the integrated circuit. The reset is generated asynchronously upon assertion of a first signal and is terminated upon the assertion of a second signal. The assertion of the second signal also serves to select one of the scan modes. This system cannot be hacked by any method that enters scan mode since it is a hardware based solution.

Abstract: Provided is a test apparatus for testing a device under test (DUT), the apparatus operating at an operating frequency that is lower than an operating frequency of the DUT. The test apparatus includes a clock source which generates a clock according to the operating frequency of the test apparatus, a clock multiplier configured to multiply the generated clock source by a multiplication number which is set according to the operating frequency of the DUT and output a first clock for the DUT, a phase converter configured to shift a phase of the generated clock according to the multiplication number and output a plurality of second clocks having different phases, and a test pattern comparator configured to sequentially collect pieces of data from the DUT by sequentially applying the plurality of second clocks having different phases.

Abstract: The present invention provides a method, device, and system for testing devices under testing (DUTs). The method comprises: sending a scan activated signal and a synchronous clock signal via the second signal line, and sending a first preset signal via the serial signal line, wherein each bit of the first preset signal is transmitted to a corresponding scan chain unit in a sequence of serial connection of the plurality of scan chain units with according to the synchronous clock signal, the corresponding scan chain unit is one of the plurality of scan chain units connected serially and coupled to the plurality of DUTs via a third signal line; sending a scan deactivated signal via the second signal line, to deactivate the scan chain units from identifying and receiving the first preset signal; and sending a second preset signal via the second signal line, and sending a test signal via the first signal line.