Abstract: The system provides a relatively inexpensive raster-scan type graphics system capable of real time operation, utilizing logic-enhanced pixels within an image buffer, permitting parallel (simultaneous) calculations at every pixel. A typical implementation would be as custom VLSI chips. Each cell of the image buffer corresponds to a pixel of the display, and a processor at each cell enables calculation of the pixel color and the like for each polygon in the image covering that same pixel (cell) of the display. In the sequence of most general applications, each polygon is operated upon in sequence, and the image is built up as the polygons are processed without the necessity of sorting.

Abstract: A data processing system which includes a central processing unit (CPU) to which is connected an I/O bus and a memory bus is disclosed. The data processing system further includes an I/O controller and a video control section. The I/O controller includes a terminal control section which is connected to the CPU through an RS232 Cable, an I/O control section which is connected to the I/O bus over a single line and a single processor for managing both the terminal control section and the I/O control section. The I/O control section includes a plurality of interface and control subsystems each for use with a separate peripheral device and an I/O bus interface and control subsystem. The terminal control section includes a video control section interface through which data is sent directly to the video control section over a separate line, and a keyboard interface for interfacing the terminal control section to a keyboard.

Abstract: A memory control apparatus for a data processor using a virtual memory technique includes two cache memories one for storing a portion of the instructions located in the main memory (MMU), the other for storing a portion of the operand data located in main memory. A separate translation look aside buffer (TLB) is connected to each cache memory, with the TLB connected to the cache memory storing instructions operating to translate logical addresses to real addresses in the MMU storing instructions, while the TLB connected to the cache memory storing operand data operating to translate logical addresses to real addresses in the MMU storing operand data.

Abstract: A method of generating a backup copy of a database system. Modifications made to the database since the generation of a prior backup copy are summarized in a bit map on a page basis. When the next backup copy is made, only modified pages are transmitted and merged with the prior copy. Plural backup passes are made. New modifications are allowed to occur to the database on all but the last pass. Any database modification made at an address that has already been examined during a pass is backed-up during the next pass. Modifications are locked out at the beginning of the last pass to allow the final generation of a consistent and complete backup copy.

Abstract: A parallel binary adder has several blocked adders, wherein numbers of bits of adders are selected to be larger in higher order blocks than lower order blocks, thereby addition in all blocks will finish at the same time, thereby undue waiting time between the completion of the addition in several blocks can be eliminated, and thereby a faster parallel binary adder is obtainable.

Abstract: A terminal control apparatus for controlling data transfer between a terminal device and a central processor includes a terminal control unit for editing data and a communication control unit for transmission/reception of data. The terminal control unit and the communication control unit are operable independently of each other to carry out processings in parallel. In data transmission, when the terminal control unit completes the editing of a predetermined amount of data, the communication control unit transmits the edited data in parallel with edit processing of ensuing data by the terminal control unit. In data reception, when the communication control unit receives a predetermined amount of data, the terminal control unit edits the data in parallel with reception processing of ensuing data by the communication control unit.

Abstract: A system and method for manipulating a plurality of data records. Each record is comprised of a plurality of bits and is identified by a unique record address value. A portion of each record comprises a keyfield consisting of one or more sub-keyfields, each having a different order of significance. The sub-keyfield value of greatest significance of each record is utilized to enter the unique record addresses into a column of a compressed matrix memory means in a logical row corresponding to the sub-keyfield value of that record. The column entries of the set compressed matrix memory locations are then arranged in order of row position, and the column entries derived from the same row are grouped together. The process is successively repeated, separately for each group of duplicate column entries, for the sub-keyfield value of next greatest significance of each record in the group as long as at least one group of duplicate column entries remain and all sub-keyfields have not been processed.

Abstract: An improved method for indexing and accessing data stored in a computer storage system, comprising a multi-way tree structure having interconnected branch nodes and leaf nodes. The leaf nodes contain a large number of distinction bits, rather than a smaller number of search keys as known in the prior art. A distinction bit is determined by comparing two selected search keys and determining the ordinal number of the first bit that is different between the two keys. The density of distinction bit entries in the leaf nodes permits shorter access times to obtain data records in a computer storage system.

Abstract: A data processing system has an arithmetic logic unit that includes a plurality of summation units for summing an ADDEND with a AUGEND to obtain a first signal that represents the summation of the ADDEND, AUGEND and a CARRY IN. Each summation units also provides a second signal that represents the carry of the summation of the ADDEND and the AUGEND. The plurality of summation units are arranged in a second plurality of groups of less than a third preselected number of summation units with over to the carry in such that each member group has a carry a serial connection of the carry in for receipt of a carry out from a preceding group's carry out. Interdisposed between the groups is a fourth plurality of carry boost units for boosting the second signal of a preceding group prior to application to a following group.Each summation unit includes a carry advance node which is driven to a predetermined voltage when the ADDEND and AUGEND do not indicate a carry propagate condition.

Abstract: A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.

Abstract: The invention relates to a digital data processor based upon the pipeline control system, which is particularly effective when the time required for reading a microprogram is relatively short. A microcycle is based upon the time required for reading the microprogram, and the operations on the data is executed in a pipeline system by dividing it up according to the determined microcycle. This is done by providing a destination latch register on the output side of the arithmetic unit. The invention further deals with the processors in which the destination latch register is provided on the input side of the arithmetic unit, or when the destination latch register is incorporated within the arithmetic unit, and a circuit setup for avoiding any contention for a register that may develop when executing a current instruction and the next instruction is provided in accordance with an added microprogram.

Abstract: An operation processing apparatus executes an instruction accompanied by addition/subtraction for one word and halfword operands at a high speed. An expander expands the sign of a second operand in its upper halfword bits to produce an expanded second operand having the same length as that of a first operand. An arithmetic unit operates the first operand and the expanded second operand.

Abstract: In a method for obtaining common mode information and common field attribute information for a plurality of card images belonging to a "box" in a data processing system, fixed information and field indicating information are written into a mode image buffer and the content of the mode image buffer is displayed on a display unit. The field indicating information written into the mode image buffer is analyzed to make field definition information tables, and a field name, for each field, is detected to make a field name table. By sorting and merging the contents of the field definition information tables and the field name table, a blank form is made.

Abstract: A multi-processor system includes a main storage and buffer storages of multi-layered hierarchy, which share the main storage. A plurality of storage controllers, each of which contains a first buffer storage, are connected with the main storage and at least one processor containing a second buffer storage is connected with each of said storage controllers. The directory of the first buffer storage contains an exclusive bit indicating whether the data existing in the first buffer storage are only one copy from the main storage or not and thus reduces the repetition of requests for the data coincidence control between different storage controllers. Each of said storage controllers contains a directory having the same content as that of the directory of the second buffer storage of the associated processor and effects the data coincidence control between different processors for store request produced in the processors.

Abstract: Disclosed is a computer system (FIG. 1) that is operable with any multiplexed-address memory (200) within a size range of 2.sup.N to 2.sup.N+R memory locations (211). The system has a memory of 2.sup.S locations selected from the predetermined range, and the memory has S/2 multiplexed address input terminals (231). Address bits forming a memory address, generated for example by a processor (400), are multiplexed by a memory controller (300) onto N/2+R address output terminals (314) in two sets of N/2+R address bits. The address bit sets have at least R/2 bits in common. An address bus (250) transports the multiplexed address bits to the memory. The bus has N/2+R address leads (251) connected to the output terminals of the memory controller. S/2 of those address leads are also connected to the address input terminal of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals.

Abstract: An execution processing device for executing variable length floating-point data of exponent part designated by two or more kinds of representation systems and fixed length floating-point data of exponent part designated by two or more kinds of representation systems, includes a converting circuit which converts the data of various representation systems into a common representation system which is capable of expressing the data in a common data form responsive to an operation mode that is provided to discriminate the various representation systems at the time of reading and operating on the data of the various representation systems stored in a storage unit according to the same load instruction. An arithmetic unit introduces the data converted by said converting circuit into the common representation system, which performs the operation designated by the same instruction, and which produces the operation result as the data of the common representation system.

Abstract: An electronic database search system can identify database records having textual expressions that match, or are similar to, an operator-designated search expression. The system features a mechanism for transforming linguistic expressions, e.g., words, into linguistically salient word skeletons. Skeletal modification and suffix stripping features are employed to enhance expression-matching qualities of the word skeletons and to reduce data storage requirements.

Abstract: A multiprocessor system consisting of a plurality of slave processors and a master processor each connected by a bus to a common memory. Message transfers are implemented by the master which scans one-byte areas in the common memory-each slave processor only being able to load a pointer to one said one-byte areas.Contention problems are prevented because once a remote processor has loaded information to its one byte area it must pass control of the bus to another processor. The system is fast because the master does not waste time looking at empty memory.

Abstract: A supervisory circuit for use in an integrated circuit to supervise the program execution of a processing unit is disclosed. The processing unit generates a restart signal at a particular duty cycle under proper program execution conditions and at an undesirable duty cycle under improper program execution conditions. The supervising circuit includes a capacitive or like circuit element for converting the restart signal into a signal representative of the duty cycle thereof and compares the generated signal to a reference window comprising upper and lower reference values. Should the generated signal exceed the boundaries of the window reference, a corresponding control signal is generated to change the circuit conditions and generate a reset signal to the processing unit to govern the program execution thereof to a prespecified point from which point program execution may continue upon removal of the reset signal.

Abstract: A high performance pipelined virtual first-in first-out stack structure having a data stack portion and a split control stack portion is described. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.