Abstract: Depth information is stored in a 2-port memory having a random port and a serial port. The depth information is read out from the serial port of the 2-port memory and is supplied to an integrated circuit. The integrated circuit performs pipeline processing by using the depth information read out from the 2-port memory. If write-in is necessary as a result of the pipeline processing, the processed depth information is supplied to the random port of the 2-port memory, and the depth information is stored once again in the 2-port memory.

Abstract: Apparatus for an array of digital signal processors that can be reconfigured as a one-dimensional or as a two-dimensional array; and method and apparatus for compensating for inconsistent time delays in signals processed by n-dimensional arrays of signal processors.

Abstract: Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.

Abstract: In a central processing unit, one write address is made to correspond to a pair of registers, and when an instruction output from an instruction decoder is a data transfer instruction to either one of the above-mentioned pair of registers, the data held in one of the above-mentioned pair of registers is kept to be held in either register of the above-mentioned pair of registers and the data from the internal data bus is transferred to the remaining register of the pair of registers, and in response to a read instruction, data is transferred from each register to the internal data bus without changing the contents of the other register.

Abstract: A multiprocessor control system adapted to a multiprocessor system includes a switching circuit, a control stage circuit, a switching mode setting circuit, and a switching control circuit. The switching circuit selectively switches a second group of instructions supplied from first execution units to select the second group of instructions relating to one of the first execution units. The control stage circuit includes a plurality of register stages used for controlling a pipeline process. The control stage circuit sequentially stores the second group of instructions relating to the selected one of the first execution units in the register stages and outputs, for every register stage, a state indicating signal indicating state information regarding the corresponding register stage. The switching mode setting circuit generates a mode setting signal used for selecting one of a plurality of switching modes each defining a timing with which switching by the switching circuit occurs.

Abstract: An electronic digital computer has a warning facility for indicating activity and operation, or lack of same, of the central processor in the system. It is done by providing a signal indicative of continuing operation of the central processor to activate an indicator circuit. The indicated circuit utilizes an RC circuit for maintaining a high level through a high comparator when the processor is operational. When the central processor becomes non-operational, the capacitor discharges to a point where a low comparator responds, causing the capacitor to begin charging to its high value. The associated circuits, using this feature, maintain an LED in the active stage until such time as there is no signal indicating continuing operation of the central processor, at which time the LED begins an approximate 50% duty cycle resulting in a blinking indicator.

Abstract: A circuit by which an SWI instruction held in a memory circuit is switchedly input in response to a signal supplied externally is provided in a processor, whereby the substitution of a program word can be realized using such an internal circuit, so that a high-speed and reliable break in program excution can be effected. Moreover, an interrupt function separate from normal interrupts is established by setting a specified operation mode, whereby, when a data processor is used as an emulator, the break of a user program including the ordinary interrupt processes can be easily effected by utilizing the special interrupt function. Also, by additionally providing the function of delivering out a signal indicative of the break status, an external circuit can be simplified.

Abstract: A memory system for the transfer of a block of data, wherein the transfer of data can begin at a starting address anywhere within the block. The block is stored on two memory chips, each having multiple parallel outputs. The two chips are addressed by a common high order address bus and different low order address bus. The low order addresses are generated such that an ordered sequence of bits, beginning at the starting address, is transferred in parallel to the register from both chips, regardless of the starting address.

Abstract: A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instruction read out from the main memory, and an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and from the main memory when the instruction is not present in the first associative memory the instruction control unit produces an output the instruction to be executed. An instruction execution unit has a second associative memory that stores operand data read out from the main memory, and an instruction executioner executing the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: A bus switching apparatus and method for multiple processor computer systems comprises a plurality of bus switches interconnected by branch buses. Each processor or other module of the system is connected to a spigot of a bus switch. Each bus switch also serves as part of a backplane of a modular crate hardware package. A processor initiates communication with another processor by identifying that other processor. The bus switch to which the initiating processor is connected identifies and secures, if possible, a path to that other processor, either directly or via one or more other bus switches which operate similarly. If a particular desired path through a given bus switch is not available to be used, an alternate path is considered, identified and secured.

Abstract: The present invention is capable of registering and reading out a logical element for which the state of the output pin changes. The system includes an input side reading out circuit for reading out the kind of logical element and the states of all the input pins thereof, a decision circuit for deciding the presence of the output pin that the status change is produced on when a logical operation is carried out according to the kind of logical element, an output side reading out circuit for reading out the information related to the logical element of the output pin producing the status change, and an exchange sending circuit for sending each information read out from the output side reading out circuit to the desired registering and reading out circuit for precise high speed logic simulation of a large scale logic circuit containing MOS-type logical elements.

Abstract: A system and method for nodes to obtain access to a bus. In this arbitration method, a central arbiter selects a particular node and issues a conditional grant. The conditional grant is transmitted before it is determined whether access to the bus will actually transfer to another node. Each node contains distributed logic that examines an extend bus cycle signal to determine whether it can become a transmitter to transfer messages on the bus. When a node becomes a transmitter, it generates an extend bus cycle signal to maintain access to the bus when executing a multi-cycle transfer, even though other nodes, perhaps with higher priorities, require access to the bus.

Abstract: A vector register provides the capability for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.

Abstract: A date checking system optionally attached to a host device like a typewriter has two buffers, a predetermined cut-out rule and a dictionary ROM. A data queue from the host device is temporarily stored in one of the buffers, and then one word is cut out therefrom by cut-out codes like a space or punctuation mark to be stored in another buffer, where the word is locked up in the dictionary ROM to determine if the spelling thereof is correct.

Abstract: In a memory module, signature data identifying the configuration of memory in that module is multiplexed onto a general memory data bus along with memory data normally transferred during memory access operations. A plurality of such memory modules can be combined in an automatic sizing memory system using a configuration status register to store configuration data for each of the memory modules. The configuration status register can include several independent status registers, each corresponding to a different memory module. Each of the status registers can contain a base address identifying the starting address of each of the modules. Elements in the configuration status register can then compare the addresses received from a central processor unit to the base address data in each of the status registers to select the memory module containing the location corresponding to each address. The status register can also contain validity and error indicators.

Abstract: A multiprocessing system is presented having a plurality of processing nodes interconnected together by a communication network, each processing node including a processor, responsive to user software running on the system, and an associated memory module, and capable under user control of dynamically partitioning each memory module into a global storage efficiently accessible by a number of processors connected to the network, and local storage efficiently accessible by its associated processor.

Abstract: A program routine vectoring system for use in a data processing system has a central processing unit and input circuitry for receiving interrupt information.

Abstract: Proceeding from a known method and apparatus for expanding the address for accessing a main memory by a central controller of a switching system, a determination is made in a comparator as to whether the address information of the high-order address lines or address registers of the expansion device with respect to a preceding main memory access changes in comparison to the current main memory access. When coincidence is present, the high-order portion of the main memory address in the preceding main memory access stored in an address register is immediately used for the formation of the overall main memory address.

Abstract: A host computer functions as one or more variant systems. The host computer stores one or more system control programs, SCP's, where each SCP is provided for production operation of the host computer. The host computer includes common control means for all of the SCP's for controlling the host computer. The host computer also includes extended control means responsive to the one or more SCP's to make the host computer appear as one or more variant systems. The extended control means in the host computer ensures efficient operation of the host computer during production runs of each one or more of the SCP's.