Abstract: A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.

Abstract: An equalizer comprises a hard decision block which feeds an FEC block and a shift register, which uses past estimates during a first iteration. The output of the FEC block is fed back to the shift register during a subsequent iteration to fully remove any inter chip interference.

Abstract: A data transmission device for serial, synchronous transmission of data includes a master device and a slave device which can be linked by at least one data transmission line and a clock signal line. The master and slave devices can be linked by an additional ready signal line for transmitting a ready signal from the slave device to the master device. When the slave device has completed a data reading operation, a ready signal can be generated for the master device. The master device is able to initiate a further writing operation to the slave device only after receiving the ready signal from the slave device. Suppression of interference by the slave device may be enhanced.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: A system to communicate digital data symbols with higher than QPSK modulation comprises a transmitter and receiver. The transmitter comprises, a modulator and circuitry to split and encode the data into a first block of more significant bits and a second block of less significant bits for modulating by. The receiver receives digital data bits by iterative determination of soft estimates of bits followed by a hard decision as to what bit was intended, and comprises a first processor to provide first soft estimates of bits of the received signal, and a second processor to decode the first soft estimates and to provide second soft estimates of the bits.

Abstract: A channel estimator for use in wireless local area networks (WLAN's), characterized in that a channel estimation controller with a simplified recursive least square (RLS) algorithm and a data-reconstructor are employed to adjust the channel response in frequency domain during the delivery of a signal packet. Such adjustment is adaptively performed at anytime during the delivery of a signal packet so as to achieve fast convergence as well as accurate channel estimation.

Abstract: 8PSK modulation methods and apparatuses are provided. In a first embodiment, product factors of symbol vectors and a coefficient of a shape filter are stored in a table and compressed by 8 times based on a law of a trigonometric function, wherein a method of table looking-up is used to replace a multiplication operation. In a second embodiment, all states of 8PSK modulation are stored in a table after shape filtering, and then the data of the states stored in the table are compressed based on a corresponding relationship of a law of a trigonometric function and an electrical level diversity, and then a table looking-up operation is performed. In a third embodiment, new modulated vectors are stored in a modulated phase table after simple 8PSK modulation and phase rotation, the modulated phase table is compressed by 4 times, and new modulated vectors are obtained by a table looking-up operation and data processing. Then, shape filtering is performed by utilizing a RAM coefficient filter.

Abstract: In one embodiment, an apparatus includes a correlator unit that generates a set of correlator outputs and a codeword selector coupled to the set of correlator outputs to determine a received codeword therefrom. The correlator unit may have reference signals pre-compensated with intra-codeword interference.

Abstract: A multichannel receiver for effectively receiving multichannel signals at the same time without any restrictions in the symbol timing and channel interval of modulated signals. A quadrature detector of the multichannel receiver includes first and second multipliers. The first multiplier multiplies a received signal by a real number axis signal generated from a quadrature carrier oscillator. The second multiplier multiplies a received signal by an imaginary number axis signal. The quadrature detector converts a carrier of a center signal of odd signals into a DC component of zero frequency, and converts the center signal into a complex baseband signal, and at the same time converts carrier signals other than the center carrier signal into a complex IF signal symmetrical to the DC component of zero frequency. ADCs (Analog-to-Digital Converters) convert the complex IF signals into complex IF digital signals.

Abstract: A transceiver is disclosed. The transceiver includes a plurality of digital signal streams, wherein at least one digital signal stream is coupled to another of the digital signal streams. A transform block transforms a plurality of the digital signal streams from an original domain into a lower complexity processing domain. A processor joint processes the transformed digital signal streams, each joint processed digital signal stream being influenced by other digital signal streams. An inverse transform block inverse transforms the joint processed signal streams back to the original domain. A method of joint processing a plurality of digital signal streams is also disclosed. A first act of the method includes transforming a plurality of the digital signal streams from an original domain into a lower complexity processing domain.

Abstract: A method and apparatus for multi-path channel characterization in a Direct Sequence Spread Spectrum based wireless communication system is provided. The multipath channel is modeled as a tapped delay line FIR filter with L taps corresponding to L paths. A pre-defined training sequence is transmitted over the multipath channel. The received signal is sampled and cross correlations are computed between the samples obtained and the spreading sequence for various time lags to obtain the symbol boundary. Thereafter, a desired set of L cross correlations for L time lags around the symbol boundary is estimated. For this, all the L possible sets of L cross correlations for L time lags around the symbol boundary are considered. The energy in the cross correlations corresponding to each considered set is calculated. The set of L cross correlations having the maximum energy is selected for tap computation. The tap coefficients are estimated by solving a set of L simultaneous linear equations.

Abstract: Timing recovery device for recovering a symbol clock from a received broadcasting signal, wherein a sign is used as a timing error, which is extracted from a result of multiplication of a difference of two symbol samples and an intermediate sample thereof, thereby very great average gain with respect to the timing error, that shortens a time period required for capturing the timing error. Particularly, since the very great average gain is obtainable even in a case a 0 dB presents, the timing offset can be captured at a short time period.

Abstract: The present invention provides an efficient means of estimating symbols transmitted in a multi-user environment in overloaded or super-saturated conditions by employing a deferred decorrelating decision feedback detector. In one embodiment, the present invention comprises a parameter estimation unit, filter bank, overloaded whitener and decision tree-based hypothesis testing. Parameter estimation defines the matched filter bank, whitening filters, and the terms of the hypothesis testing module. The whitening filter partially decouples co-channel interference and partially whitens the noise. The decision tree approach defers decisions until more evidence is accumulated and is a generalization that encompasses the jointly optimal maximum likelihood detector as well as the simpler decision feedback detectors.

Abstract: The PL signal of a PL portion is multiplied by gain factor ?c in a multiplier(109) and the data of a data portion is multiplied by gain factor ?d in a multiplier(110). These gain factors ?c and ?d are controlled in a weight controlling circuit (112). The PL signal and data thus multiplied by gain factors are added in an adder (111) and become an added PL signal. This added PL signal is output to a delay profile generation circuit (113). In the delay profile generation circuit (113), a delay profile is generated using the added PL signal. The delay profile is output to a path selection circuit (104) where path search is performed, and the information of selected reception timings are output to a RAKE combining circuit (105) and a channel estimation circuit (115). By this means, iterative path search and channel estimation can be performed with accuracy even when receiving signals where channels of different transmission power ratios are multiplexed.

Abstract: A method and apparatus for deriving the channel estimation within a packet based transmission system having a predetermined number of tones (N), wherein each channel has a channel order (L). A first method includes precomputing, from the long sequence (X) of a received signal, a channel estimation matrix (R?1) having a dimension of width and length equal to the channel order (L) and storing one fourth of the channel estimation matrix (R?1) since the channel estimation matrix (R?1) is centrosymmetric. Advantageously, precomputing and storing a fourth of the channel estimation matrix (R?1) saves time and complexity. In a second method, the bit-width requirement for fixed precision requirements regarding implementation in hardware is reduced wherein a channel estimation matrix (G) having dimension of width equal to the number of tones (N) and length equal to the channel order (L) is precomputed and stored.

Abstract: A signal level detector to detect the level of 1-bit digital signal is provided. It includes a level detector (12) supplied with a sequence of 1-bit digital signals decoded by an audio decoder (5) and which counts the number of 0 (zeros) or 1 (ones) included in the row of a predetermined number n of 1-bit digital signals to detect the level of the 1-bit digital signal, and an indication unit (13) to indicate the signal level detected by the level detector (12).

Abstract: The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator.

Abstract: Clock and data recovery circuitry includes an interleaved sampler having multiple integrators, where at least one of the integrators integrates the input data for at least two unit intervals (UIs). One embodiment includes a four-way interleaved sampler, where each integrator in the sampler integrates the input data for two UIs, where each integrator is sampled at or near the middle of its two-UI integration cycle. In an exemplary 10-GHz system, the reset cycle of each integrator may begin many tens of picoseconds after the data is sampled. Since the signal is sampled near the center of the integration cycle and is not highly proximate to the time of the integrator reset, the latch signal has a window of uncertainty extending into the length of a data bit cell with little possibility of latching erroneous data. The sensitivity of the clock recovery circuitry may be optimized by centering the latch function over the time of highest signal level, thereby maximizing signal-to-noise ratio.

Abstract: A forward link transmitter in a sectored cell includes a baseband processor having traditional baseband signal digital processing circuitry in addition to including a digital hybrid matrix (vector and delay compensated transformation module) whose phase and amplitude (vector) and delay may be adjusted to compensate for downstream errors that are introduced and detected by a feedback circuit. Accordingly, the baseband processor, by monitoring an output of an analog hybrid matrix producing modulated and amplified radio frequency (RF) signals just prior to propagation from an antenna, can determine errors produced by the analog circuitry including the analog hybrid matrix and may compensate for the same by introducing an amplitude, phase and delay adjustment (in the digital domain) into output digital waveform signals to compensate for the error introduced downstream to the baseband processor.

Abstract: A method and device to equalize a signal received by a receiver after having traveled through a transmission channel, the signal including one data block and several probes located on either side of the data block. The method includes a step in which the impulse response of the channel is estimated before and after a data block n in taking account of the probes (Probe n 1 and Probe n) located on either side of the data block n and also of the probes that precede and follow the Probes n?1 and Probe n, the probes being weighted and combined with one another.