Abstract: A code rate adaptive encoding/decoding arrangement and method for a pulse code modulation system comprises a code rate adaptor and a code capacity meter to dynamically produce a code rate adaptive signal for the code length of the pulse code modulation adaptive to actual situations during the encoding/decoding process.

Abstract: A method of estimating initial channel quality in a receiver when allocated a new channel in order to select an optimal codec mode in a multi-rate service is disclosed. One implementation initially fills the filter state with the first received channel quality measurement. Another embodiment proportionally fills the entire filter state with the calculated channel quality measurements. Yet another embodiment uses the hysteresis and threshold parameters in conjunction with the initial codec mode to calculate an initial fill value for the filter state.

Abstract: The present invention provides a filter circuit, related method of operating the filter circuit and a digital signal processing circuit incorporating the same. In one embodiment, the filter circuit includes a conditioning stage, operable at a rate corresponding to an input signal to be sampled, configured to derive an intermediate signal from the input signal as a function of a parameter. The filter circuit further includes an output stage, operable at a sampling rate, configured to derive a sampled signal as a function of the intermediate signal where the parameter is adapted to govern characteristics of a frequency response associated with the sampled signal.

Abstract: A coding method for modulating carrier signals with 16 different digital states (4 bit signals) possesses a high synchronicity robustness and an at least partially improved coding gain. The coding parameters are obtained by the following steps: a) using a 2 ASK/8 PSK coding; b) choosing a convolutional code and determining all possible code word sequences with the free distance of the convolutional code; c) producing possible mappings by allocating a partial quantity of the 2 ASK/8 PSK channel bits to subsets; d) choosing the mapping at which, after determination of the optimum radii of the two amplitudes for every possible mapping, the resulting minimum Euclidean distance takes a maximum value between two possible subset sequences code word sequence.

Abstract: A method of determining imbalance in a vector signal modulator. First and second channels of a vector signal modulator are stimulated with a multi-tone signal having a power versus frequency spectrum having numerous of frequencies. In response to the stimulation, an output of the vector signal modulator is measured. The first and second channels are simultaneously stimulated with a multi-tone signal having essentially the same characteristics as the one used when separately stimulating the channels. Data collected from both the separate and simultaneous stimulations are used to calculate imbalance versus frequency of the vector signal modulator. Alternatively, two channels of a vector signal modulator are simultaneously stimulated with first and second multi-tone signals. The first and second multi-tone signals have tones at main frequencies and at first and second offsets thereto, respectively. Output measurements are then made and imbalances are calculated.

Abstract: The present invention uses a novel adaptive soft decision device in order to jointly optimize decision device and DFE operation. The soft decision device receives the input and output samples of the slicer and generates a feedback sample by non-linearly combining them with respect to a single decision reference parameter. Moreover, the soft decision device provides novel error terms used to adapt equalizer coefficients in order to jointly optimize decision device and equalizer coefficients.

Abstract: The receiving device of the invention contains a correlational operation unit that executes a correlational operation between a first modulated signal having a spread-spectrum modulation applied and a first spread-spectrum signal string to output a correlational signal, and a decision circuit that decides an amplitude value of the correlational signal to output a decision signal. The decision circuit is composed of: a first detector that outputs a first detection signal when it detects that a value of the first correlational signal exceeds the first threshold, a second detector that outputs a second detection signal when it detects that the value of the first correlational signal exceeds the second threshold, and a detected signal selector that outputs the decision signal of a first value when the first detection signal is inputted, and outputs the decision signal of a second value when the second detection signal is inputted.

Abstract: Operation of a digital subscriber line system in a power saving quiescent mode is described. A quiescent mode (Q-mode) is entered into from a steady-state or normal operation mode in which payload data is transmitted when criteria indicates that the transmitter has stopped transmitting payload data for a certain time period but that the current transmission session has not ended. A Q-mode signal is generated that uses constellation points that are used in the payload carrying state. The peak-to-average ratio (PAR) of the signal is also minimized by a PAR minimization method to find a combination of these constellation points satisfying a PAR threshold.

Abstract: A device for predistorting a transmission signal to be transmitted over a nonlinear transmission path comprises an estimator for determining an error signal depending on the transmission signal and a previously registered transfer characteristic of the nonlinear transmission path. The error signal represents an estimate of an error generated due to the nonlinearity of the trans-mission path. A time-dispersive element is provided to produce a correction signal by a temporal extension of the error signal. A combiner is provided to combine the transmission signal and the correction signal. As a result of the temporal extension of the error signal, an error signal segment in the frequency spectrum of a transmission signal transmitted by the nonlinear transmission path is shifted away from the useful frequency range of the transmission signal.

Abstract: In a signal generating circuit SG1, a 90 -degree divider 3 generates, from a local oscillation signal SLO supplied through an input terminal 1, an intermediate reference phase signal ISREF and an intermediate quadrature signal ISQR orthogonal in phase to the intermediate reference phase signal ISREF for output to mixers 6 and 7, respectively. A shifter 4 shifts the phase of the local oscillation signal supplied through an input terminal 2 by a predetermined amount to generate a shift signal SSFT for output through a divider 5 to the mixers 6 and 7. The mixer 6 mixes the input intermediate reference phase signal ISREF and the input shift signal SSFT to generate a reference phase signal SREF. The mixer 7 mixes intermediate quadrature signal ISQR and the input shift signal SSFT to generate a quadrature signal SQR. With this, it is possible to provide a signal generator capable of generating highly-accurate, high-frequency reference phase signals and quadrature signals.

Abstract: The invention relates to a method for transmitting data streams where transmission/reception devices (LTU, NTU) deactivated to a standby state are activated by performing a warm start sequence, with transmission line parameters being determined (S103) using an exchange-end transmission/reception device (LTU) following provision of a subscriber-end transmitted signal, transmission line parameters being determined (S104) using a subscriber-end transmission/reception device (NTU) following provision of an exchange-end transmitted signal, echo cancelation being realigned (S105) using a subscriber-end transmission/reception device (NTU) following provision of a subscriber-end transmitted signal, and/or echo cancelation being realigned (S106) using an exchange-end transmission/reception device (LTU) following provision of an exchange-end transmitted signal.

Abstract: A distributed clock circuit for clocking high speed data at various different physical locations on a chip while improving setup and hold times. The clock circuit includes a master delay lock loop (DLL) circuit configured to lock a global clock signal with a first data signal, and output a clock delay control signal when the global clock signal is locked. The clock circuit further includes one or more slave DLL circuits, coupled to receive the clock delay control signal to lock a local clock signal with a local data signal, wherein the local clock signal is based on the global clock signal.

Abstract: A method of transmitting adaptive modulation signals using space-time block code matrix from a plurality of antennas, the method comprising the steps of: changing adaptively the number of transmission repeat times of the matrix according to a propagation condition, transforming modulation signals at each transmission repeat timing from each antenna by using the matrix, and sending the transformed signals at each transmission repeat timing from each antenna.

Abstract: A method and apparatus for determining an optimum modulation scheme for a retransmission in a communication system supporting HARQ. When two modulation schemes are available, at an initial transmission, information is modulated in the lower-order modulation scheme if a first MPR is less than a first threshold, and in the higher-order modulation scheme if the first MPR is greater than or equal to the first threshold. Here, an MPR is determined by an EP size, the number of available Walsh codes, and the number of slots per sub-packet that are used for a transmission. To select one of the modulation schemes for a retransmission, a second MPR is calculated using an EP size, the number of available Walsh codes, and the number of slots per sub-packet that are used for the retransmission. If the first MPR is equal to or less than a second threshold greater than the first threshold, the lower-order modulation scheme is selected.

Abstract: In an auto baud system and method, the baud rates between two communicating devices are synchronized by timing the transmission of a plurality of bits by counting the cycles of a reference clock. The number of cycles counted is then divided by the number of bits counted over and any remaining cycles are distributed evenly across the data being transmitted or received. The interface of the circuit is preferably implemented as a single pin, open drain interface which can be connected to an RS-232 communications link using external hardware.

Abstract: An apparatus for providing a multi-mode interface between a baseband receiver and radio frequency (RF) circuitry. According to a preferred embodiment of the invention, the apparatus includes a first differential-to-single-ended converter, a second differential-to-single-ended converter and an analog-to-digital converter. The first differential-to-single-ended converter receives an incoming differential current pair to be converted into a first single-ended voltage signal. The second differential-to-single-ended converter receives an incoming differential voltage pair to be converted into a second single-ended voltage signal. Further, the analog-to-digital converter selectively receives an incoming single-ended voltage signal, the first single-ended voltage signal, or the second single-ended voltage signal to be converted into a digital signal to be further processed by the baseband processor.

Abstract: A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.