Patents Examined by B. James Peikari
  • Patent number: 7197607
    Abstract: A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: March 27, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 7193916
    Abstract: A recording apparatus for facilitating data erasure operations involving data recorded on a recording medium. Each piece of data recorded on the recording medium may be examined to determine whether it is re-recordable by determining whether the data is already stored in another storage medium. When data erasure is requested, erasure processing may be controlled in accordance with the result of the determination. For example, original data based on data captured by a microphone or a camera (namely, non-re-recordable data) may not be erased (without specific approval by the user). Conversely, re-recordable data copied from another recording medium such as a CD may be erased.
    Type: Grant
    Filed: June 16, 2004
    Date of Patent: March 20, 2007
    Assignee: Sony Corporation
    Inventors: Teppei Yokota, Nobuyuki Kihara
  • Patent number: 7194561
    Abstract: The present invention provides for the scheduling of requests to one resource from a plurality of initiator devices. In one embodiment, scheduling of requests within threads and scheduling of initiator device access is performed wherein requests are only reordered between threads.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: March 20, 2007
    Assignee: Sonics, Inc.
    Inventor: Wolf-Dietrich Weber
  • Patent number: 7194576
    Abstract: A method and system for improving fetch operations between a micro-controller and a remote memory via a buffer manager in a disk drive control system comprising a micro-controller, a micro-controller cache system having a cache memory and a cache-control subsystem, and a buffer manager communicating with micro-controller cache system and remote memory. The invention includes receiving a data-request from micro-controller in cache control subsystem wherein the data-request comprises a request for at least one of instruction code and non-instruction data.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 20, 2007
    Assignee: Western Digital Technologies, Inc.
    Inventor: William B. Boyle
  • Patent number: 7194532
    Abstract: In a management information generating step, management information of disks opened by a plurality of peers connected through a network is generated. In an access request step, another peer which opens a disk is selected from the management information, and a file is requested to be stored or read. In an access execution step, the file is stored or read in response to the storage request or the read request from the other peer.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: March 20, 2007
    Assignee: Fujitsu Limited
    Inventors: Shinichi Sazawa, Yuichi Sato
  • Patent number: 7191309
    Abstract: A method of operating a processor includes concatenating a first word and a second word to produce an intermediate result, shifting the intermediate result by a specified shift amount and storing the shifted intermediate result in a third word, to create an address.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: March 13, 2007
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Matthew I. Adiletta, William Wheeler, Debra Bernstein, Donald Hooper
  • Patent number: 7191305
    Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: William D. Corti, Joseph O. Marsh, Michael Won
  • Patent number: 7188230
    Abstract: A method for assuring the integrity of stored data in a storage system is provided. At a specified time at which further writes to a desired portion of the stored data are to be precluded, a hash value is calculated for the desired portion of stored data. At a later time, retrieval of the stored data is performed and the hash value recalculated. A comparison of the former and present hash values reveals whether the data has remained unchanged.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: March 6, 2007
    Assignee: Hitachi, Ltd.
    Inventor: Nobuyuki Osaki
  • Patent number: 7188224
    Abstract: A highly-convenient content duplication management system for allowing users to duplicate a content as long as the duplication is in compliance with a given usage right. In the system, a request destination device stores a content and a permitted number of duplications of the content. In response to a duplication request, the request destination device judges whether or not the request source device is an in-group device that belongs to the same group as the request destination device. When judging that the request source device is an in-group device, the request destination device transmits the content together with a permitted number that is equal to or smaller than the currently stored permitted number. The request destination device then updates the currently stored permitted number by subtracting the permitted number transmitted.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: March 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuusaku Ohta, Hiroki Yamauchi, Masaya Miyazaki, Natsume Matsuzaki, Toshihisa Abe
  • Patent number: 7185164
    Abstract: A method for rearranging a logical volume including arranging a logical volume rearranging program on a particular server and using the logical volume rearranging program to acquire server/storage mapping information from each server and performance information from each storage subsystem. Moreover, the logical volume rearranging program acquires request I/O performance and a rearranging rule for each application set by a user. Furthermore, the logical volume rearranging program determines a destination by using the logical volume rearranging destination parity group specified by the user according to the aforementioned information, and rearranges the logical volume according to the storage subsystem performance and the request I/O performance of each application.
    Type: Grant
    Filed: April 30, 2004
    Date of Patent: February 27, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Takato Kusama, Tatsundo Aoshima, Kei Takeda
  • Patent number: 7185149
    Abstract: A cache memory device with a cache section, which is provided between a CPU and a main memory and operates as a fast buffer memory, has a capability of storing input data in the cache section when attribute information affixed to the input data indicates a predetermined attribute.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: February 27, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Atsushi Okamura
  • Patent number: 7181590
    Abstract: A method and system for allowing a multi-threaded processor to share pages across different threads in a pre-validated cache using a translation look-aside buffer is disclosed. The multi-threaded processor searches a translation look-aside buffer in an attempt to match a virtual memory address. If no matching valid virtual memory address is found, a new translation is retrieved and the translation look-aside buffer is searched for a matching physical memory address. If a matching physical memory address is found, the old translation is overwritten with a new translation. The multi-threaded processor may execute switch on event multi-threading or simultaneous multi-threading. If simultaneous multi-threading is executed, then access rights for each thread is associated with the translation.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Sailesh Kottapalli, Nadeem H. Firasta
  • Patent number: 7181573
    Abstract: In response to receiving a request to perform an enqueue or dequeue operation a corresponding queue descriptor specifying the structure of the queue is referenced to execute the operation. The queue descriptor is stored in a processor's memory controller logic.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Gilbert Wolrich, Mark B. Rosenbluth, Debra Bernstein
  • Patent number: 7177988
    Abstract: Provided is a system and method for a modem including one or more processing paths. Also included is a number of interconnected modules sequentially arrayed along the one or more paths. Each module is configured to (i) process signals passed along the paths in accordance with the sequence and (ii) implement predetermined functions to perform the processing. Further, each of the modules has a particular degree of functional programmability and the degrees of functional programmability monotonically vary in accordance with the sequence.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: February 13, 2007
    Assignee: Broadcom Corporation
    Inventors: Gregory H. Efland, Jeff Z. Guan, Gong-San Yu
  • Patent number: 7174422
    Abstract: In general, in one aspect, the disclosure describes a data storage device that includes a device interface for receiving data access requests, more than two disk drives having platter sizes less than 3.5 inches in diameter, and a controller that accesses the disk drives in response to the received data access requests.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 6, 2007
    Assignee: EMC Corporation
    Inventors: Michael Kowalchik, John Cardente
  • Patent number: 7174421
    Abstract: A hard drive retrieves critical data determined to be requested by a host device in the near future and stores it in cache. The hard drive provides the critical data to the requesting host upon receiving the request, thereby eliminating the time required to respond to the request due to media accessing. The critical data is retrieved upon the occurrence of a critical event. The critical data may be related to power-on of the computer, such as boot sector FAT system data. Thus, the cache of the present invention may use old data rather than new data or the last data accessed.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: February 6, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Richard M. Ehrlich
  • Patent number: 7174436
    Abstract: In a multi-processor, multi-memory system, a technique designates portions of a local memory as being regions to be shadowed. A shadow control unit detects write operations to those regions designated for shadowing. The shadow control unit then executes a cloning of a write operation designated for a local memory region to be shadowed and provides the cloned data to a memory space in system memory which corresponds to the local memory region which is being shadowed.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: February 6, 2007
    Assignee: NVIDIA Corporation
    Inventors: Brian K. Langendorf, Christopher W. Johnson, Franck R. Diard
  • Patent number: 7171520
    Abstract: The present invention relates to a cache flush system and the method for a cache flush performed in cache memory against at least one corresponding prescribed event in a multi-processor system. Embodiments of the present invention can reduce or minimize loads of a processor bus by performing memory read of at most a prescribed size and can increase simultaneousness of cache flush against a corresponding prescribed event by performing a cache flush directly triggered by the prescribed event thereby enabling high speed and automated cache flush algorithm.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: January 30, 2007
    Assignee: LG/Nortel Co., Ltd.
    Inventors: Sang Ik Jung, Seok Jin Yoon
  • Patent number: 7167944
    Abstract: An embodiment of the present invention includes a nonvolatile memory system comprising nonvolatile memory for storing sector information, the nonvolatile memory being organized into blocks with each block including a plurality of sectors, each sector identified by a logical block address and for storing sector information. A controller is coupled to the nonvolatile memory for writing sector information to the latter and for updating the sector information, wherein upon updating sector information, the controller writes to the next free or available sector(s) of a block such that upon multiple re-writes or updating of sector information, a plurality of blocks are substantially filled with sector information and upon such time, the controller rearranges the updated sector information in sequential order based on their respective logical block addresses thereby increasing system performance and improving manufacturing costs of the controller.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: January 23, 2007
    Assignee: Lexar Media, Inc.
    Inventor: Petro Estakhri
  • Patent number: 7165154
    Abstract: A method and system of data backup for a computer system is disclosed. Full and incremental backups of data stored to a first storage device coupled to the computer system are stored to a backup storage device coupled to the computer system. The backup storage device may be remotely located and coupled via a network. Data representative of the relationship of each incremental backup to its respective parent backup is stored in a dependency data structure, preferably a tree-like structure. Different types of incremental backups may be performed to provide different data granularity. When two or more storage media are used in a rotational manner, each medium always contains a complete backup. The backup storage device is automatically managed by paring at least one of a full and incremental backup at the backup storage device automatically in accordance with a plan. The plan is preferably configured to manage an amount of available storage space at the backup storage device.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: January 16, 2007
    Assignee: Net Integration Technologies Inc.
    Inventors: David Lawrence Coombs, Ozren Papic