Abstract: A reproduced signal from a recording medium 1 is equalized at partial response (1, 0, -1) by a reproducing equalizer 3, and is converted into a reproduced and equalized signal. A clock reproducing circuit 4 issues a reproduced clock synchronized with the timing of data identification, and applies it to a phase adjusting circuit 5. A phase control signal generating circuit 6A detects a specific pattern from a reproduced digital signal issued from an A/D converter 7, and the advance or delay amount of phase of the reproduced clock is detected by the amplitude or distribution of the sampling value. This phase deviation amount is given to the phase adjusting circuit 5 as a phase control signal. The phase adjusting circuit 5 given a delayed clock to the A/D converter 7, and controls to A/D convert the reproduced signal at correct timing.

Abstract: A method and apparatus for non-linear quantization of a signal that utilizes two or more lowresolution analog to digital converters (ADCs) to allow selective increased quantization levels at desired portions of a signal. This is accomplished by using a primary ADC which provides digital output signals over a first predetermined range, and at least one secondary ADC which provides digital output signals over a smaller predetermined range for the same input values. Accordingly, any secondary ADCs have a smaller quantization step size than the first, and are utilized when finer resolution is desired. The ADCs are kept in alignment by periodically comparing the digital values produced by the ADCs for a known input analog value.

Abstract: A circuit (10) and method for minimizing nonlinearity errors in an oversampled data converter (40) resulting from errors in the intended values of components (42-49) of the converter (40). An adder section (11) is used to add a digital input sample to a previously existing sum generated from an immediately preceding digital input sample. A resulting sum is converter from binary code to thermometer code by an encoder (20). Combinatorial logic (24) is used to provide control signals for controlling switching of the components in a manner which both converts the nonlinearity error to a noise error and frequency shifts the noise error out of a frequency passband of the converter to higher frequencies where the error is subsequently filtered.

Abstract: A circuit for converting a 8-bit .mu.LawPCM code into a 14-bit linear code comprising an inversion circuit receiving a 8-bit .mu.LawPCM code for outputting a 8-bit inverted signal. A 6-bit signal is obtained by putting a bit of "1" at a place lower than the least significant bit of less significant four bits of the 8-bit inverted signal by one bit and another bit of "1" at a place higher than the most significant bit of the less significant four bits of the 8-bit inverted signal by one bit. The 6-bit signal is shifted by a bit shift circuit in the most significant bit direction by the amount which is within a range of 0 bit to 7 bits and which is determined by second to fourth significant bits of the 8-bit inverted signal.

Abstract: A circuit for linearizing analog-to-digital output is shown in FIG. 2, with an analog signal V.sub.i transmitted by input circuit 10 is applied to an input port of an analog-to-digital converter 12 controlled by a sampling signal V.sub.s, to provide digital data V.sub.d on an "N" bit data bus 14. An analog-to-digital linearizing memory 16 storing a look-up table of digital values, is coupled to bus 14 to receive the digital data V.sub.d, and to respond to the digital data V.sub.d by providing true linear digital values from the look-up table to digital data processing system DSP 20 via an "N" bit data bus 18. A microprocessor 22 is temporarily coupled between the output port of converter 12 and the input port of memory 16 via bus 14, to serve as a switch between bus 14 and a programming memory 24 containing a table of true linear digital values V.sub.t. A known test signal is applied to input circuit 10, and true linear digital values V.sub.

Abstract: A code modulation system wherein an 8-bit input is converted to a 14-bit code by creating modulated data code tables and associating a given 8-bit input with a particular table based on the Digital Sum Variation value, the Non-Return to Zero Inverted waveform polarity, and the end-bit value of the preceding 14-bit modulated code.

Abstract: A digital time interpolation system and method for quantizing the time-difference between two digital signals. The present invention measures the time-difference between consecutive zero crossings of a user signal and a reference oscillator. The present invention outputs interpolator data, which represents this time-difference in digital form. The present invention includes a quadrature hybrid, a synchronizer, track-and-holds (T&Hs), analog-to-digital converters (ADC), an encoding circuit, and a boundary detector. The present invention also includes a system for deskewing the recorded coarse time count and the fine time value. According to the present invention, the reference oscillator is a continuous, two-phase signal having a unique pair of output values at any given instant of its period. By using this reference oscillator, the present invention accelerates conversion. The present invention uses a novel boundary detection scheme.

Abstract: An analog-to-digital converter (ADC) having two cascaded A/D stages of the parallel type wherein the analog signal is compared with a set of threshold reference voltages. The first stage develops a set of most-significant bits and produces two analog residue signals: a normal residue corresponding to the difference between the analog input and the threshold voltage below the analog input, and a second residue corresponding to the difference between the analog input and the threshold voltage above the analog signal level. These two residue signals are amplified and directed to the second A/D stage. The sum of the residue signals equals one LSB of the first A/D stage, so that the two residues supply to the second stage information about the quantization error of the previous stage as well as the quantization step size to be used to define full-scale at the second stage.

Abstract: A method and apparatus for a processor or other system device to map processor words to an associated random access memory. In one case, processor words are mapped directly to RAM with no modification. In another case, 32-bit pixels (eight bits each of red, green, blue and alpha) are converted to or from 16-bit pixels (four bits each of red, green, blue and alpha) using an ordered dithering technique. The ordered dithering technique spatially distributes the information that would otherwise be lost by truncation. This is accomplished by replacing exact pixel values with their pseudo-random average. This reduces the required pixel storage requirements by half, while maintaining a higher image quality than would be achieved by truncation alone.

Abstract: A data generator generates input data for a pulse generator from source data corresponding to a desired pulse width in order to make the pulse generator generate an output pulse having the desired pulse width. In the data generator, the source data are converted into the input data for the pulse generator based on a predetermined conversion relation; the predetermined conversion relation is varied; the width of an output pulse of the pulse generator is compared with that of a calibration pulse having a predetermined pulse width; and a conversion relation between calibration source data corresponding to a pulse width of the calibration pulse and the input data is maintained when the width of the output coincides with that of the calibration pulse.

Abstract: An integrated-circuit A-to-D converter having repetitive cells which are designed to be matched, but which are subject to uncontrolled mismatches adversely affecting performance. In the disclosed embodiment, the cells all include resistors (of equal ohmic value) carrying currents (designed to be of equal value) producing corresponding output signals. To avoid the effects of cell mismatch on the output signals, a network of equal-valued resistors is added to the circuit, with each network resistor connected between corresponding ends of adjacent pairs of the cell resistors.

Abstract: A class of lossless data compression algorithms use a RAM-based dictionary to facilitate the compression and decompression of data. The dictionary is initialized or reset at various events, such as data file boundaries, or at specific compression ratio thresholds. The average time to perform the dictionary reset is decreased by using a dictionary reset optimizer (12) to reset the dictionary without writing the DICT.sub.-- VALID fields (19) of all dictionary locations (1,2,3, . . . L) immediately upon each reset. The DICT.sub.-- VALID field in static RAM (16) is set up as an N-bit field and the optimizer includes a counter (20) for generating an N-bit DICT.sub.-- NUMBER field (22) under control of a controller (24) responsive to reset signals. During operation to compress/decompress data after a reset, the DICT.sub.-- VALID field of a dictionary location is compared to the current DICT.sub.-- NUMBER (1). If their values are equal, the DICT.sub.-- ENTRY field (18) in such location is deemed valid.

Abstract: A digital-analog converter according to the invention comprises a resistance circuit including a plurality of resistors connected in series, a switching circuit including a plurality of switching element disposed between the resistance circuit and an analog output terminal, a control-signal generating circuit for selectively turning on and off the switching elements, and a change-over circuit for switching the resistance circuit. The resistance circuit includes a first resistor having a resistance value of one half a unit resistance value and unit resistors of a unit resistance value and connected in series, the number of unit resistors provided being expressed by 2 to the (n-1)th power. The change-over circuit functions to connect resistors having a unit resistance value in parallel with selected unit resistors in the resistance circuit by means of changing switches which are selectively turned on and off by the control-signal generating circuit.

Abstract: A rate 2/5 (2,18,2) code especially suitable for use with a resonant coil overwrite technique for magneto-optical recording. Serial binary input data is converted to serial binary code data that satisfies a (2,18,2) constraint and is reconverted to the serial binary input data. An encoder receives two sequential input bits and a five-bit state vector derived from an immediately preceding encoding operation, and generates a five-bit codeword and a new five-bit state vector based on the two input bits and five-bit state vector. A decoder converts the binary code data into five-bit codewords, converts each five-bit codeword sequentially into a reassigned three-bit codeword representation, then collects sets of four adjacent three-bit codeword representations. Each reassigned codeword representation is converted to a two-bit output corresponding to a then current set of said four three-bit codeword representations, and successive two-bit outputs are reconverted into the serial binary data.

Abstract: The invention herein disclosed is a digital circuit which emulates a synchro signal in a synchro-resolver follower system for precise control of shaft position and rotation at very low rotational rates. The subject invention replaces the synchro and drive motor in a synchro-resolver follower system with a digital and analog synchro emulation circuit for generating the resolver control signal. The synchro emulation circuit includes amplitude modulation means to provide relatively high frequency resolver excitation signals for accurate resolver response even with very low shaft rotation rates.

Abstract: A ratiometric converter is provided that is comprised of a dual converter system utilizing a first converter (36) and a second converter (38). The second converter (38) is operable to receive the input voltage from a load cell (10) on sense lines (12) and (14) and compare them with an internal reference. Similarly, the first A/D converter (36) is operable to receive the reference voltage to the load cell (10) and compare it with the internal reference. The output of each of the converters (36) and (38) is then input to subtraction circuits (78) and (84), respectively, in the digital domain. In a calibration mode, switches (72) and (73) shorts the reference nodes in the load cell (10) together to determine the non-ratiometric offsets., These offsets are then stored in registers (80) and (86) for the reference voltage and the input voltage, respectively.

Abstract: The invented auto-ranging device has a signal measuring A/D converter, a range-switching A/D converter of a faster processing speed, a range-switching amplifier with variable amplification capabilities, and a processing controller which utilizes the variable amplification factors to alter the output signals from the switching A/D converter to generate signals appropriate for a scale range of a multi-range measuring A/D converter.

Abstract: A position detector device for detecting the position of a moving object includes a magnetically-recorded section on a moving surface of the moving object where multipoles are magnetized with a wave-length of .lambda., and a magnetic sensor for detecting changes in magnetic field by moving of the magnetically-recorded section. The magnetic sensor is provided with 2.sup.N (N+1, 2, 3, . . . ) pieces of signal detecting magnetic resistance elements connected to constant-current power sources and arranged at an interval of .lambda./2.sup.(N+2). The extent to which the moving object is moved is detected on the basis of electric signals outputted from these signal detecting magnetic resistance elements.

Abstract: A dual range A/D converter includes a gain matching circuit for balancing the upper end of the transfer curves of the level-dependent dual A/D signal paths of the converter so as to control crossover between the paths. One path (high gain path) is provided with signal gain that is a nominal multiple of gain applied to the other path (low gain path). A digital comparator compares the digital code word output of flash A/D converters included in the respective paths, with the output from the high gain path being scaled down to correspond to the output from the low gain path. If a difference is detected, the upper ladder reference of the flash converter in the low gain path is adjusted until the respective gain difference becomes substantially an exact multiple. When this matching is combined with black level correction, which equalizes the lower end of the transfer curves, a fully self-calibrating dual range A/D converter is obtained.

Abstract: A digital-to-analog converting unit decodes a digital input signal into a decoded signal, and selectively allows constant-current cells arranged in matrix to supply unit currents for producing an analog output signal, wherein a decoding circuit incorporated in the digital-to-analog converting unit sequentially selects the constant-current cells in such a manner that insufficient increment of current produced by one of the constant-current-cells cancels out excessive increment of current produced by another constant-current cell so that the analog output signal is improved in linearity.