Abstract: An apparatus, preferably in the form of a resolver to digital converter for converting the amplitude modulated, encoded signals into digital signals representative of the velocity and position is described. The apparatus is of the type that includes an electronic control transformer circuit for providing respective products of sine and cosine analog signals respectively times the cosine and sine of the digital position signals and for differencing the products so as to produce an analog AC error signal. The improvement comprises means for converting the analog AC error signal into a digital DC error signal and a digital accumulator for time integrating the DC error signal to generate the digital position signal. In a preferred embodiment the output of the accumulator is digitally modulated so as to provide the digital position signal as a bit-reduced feedback signal to the electronic control transformer.

Abstract: This invention relates to a code modulating apparatus and a code demodulating apparatus for digital signals such as PCM audio signal, computer data, and so on. An input signal of M bit words is divided into a plurality of data bits and the code conversion is performed for respective data bits, thereby simplifying the circuit arrangement for data conversion.

Abstract: A plurality of different reference voltages are generated. A set of differential conversion circuits has first input terminals subjected in common to an analog input signal and second input terminals subjected to the respective reference voltages, and converts differences between voltages at the first and second input terminals into differential output voltages. A first A/D conversion circuit compares the analog input signal with the reference voltages to perform a higher-order A/D conversion of the input analog signal. At least two of the differential output voltages are selected. An interval between the selected differential output voltages is divided, and divided voltages are generated in accordance with the division. A second A/D conversion circuit compares the divided voltages to perform a lower-order A/D conversion of the analog input signal.

Abstract: Method for coding a digital signal, a coder and decoder for implementing this method, a regeneration method and a corresponding regenerator. On each bit time, a detection is made of the possible presence of a binary pattern from any number "n" of binary patterns including at least two bits; the bit time is divided into "n" equal time intervals to which "n" temporal positions are associated; a correspondence is established between each of "n" binary patterns and each of "n" temporal positions; if one of the binary patterns is present, a pulse occupying a temporal position corresponding to the binary pattern is generated and the next detection for the possible presence of a binary pattern is made from the bit following the last bit of the binary pattern whose presence is detected.

Abstract: A digital signal processor comprises a code converter which converts an integer coded in a Binary Two's Complement (BTC) code to an integer coded in a Sign Magnitude Binary (SMB) code and/or a code converter which converts the SMB code to the BTC code. An integer coded in the BTC code and stored in an m-bits register is converted to an integer coded in the SMB code and input to an n-bits register, by an EXCLUSIVE OR processing of the bits with the sign bits and by supplementing a logic "1" in the less significant bit next to the least significant bit of the result of the exclusive OR operation. An integer coded in the SMB code and stored in an n-bits register is converted to an integer coded in the BTC code and input to an m-bits register, by an EXCLUSIVE OR processing of m-1 bits of magnitude bits with a sign bit. The code converters have a relatively simple construction, will not output an incorrect result, and are most suitable for processing AC signals.

Abstract: A multislope continuously integrating analog-to-digital converter for converting an analog input signal into a digital output signal where the converter employs an integrator for continuously integrating the input signal in relation to a series of reference voltages of increasing magnitude and a zero crossing detector to determine when the reference voltage has completely discharged the integrator. A counter or the like is employed for timing the duration of the discharge which corresponds to the digital equivalent of the analog input signal.

Abstract: An analog-to-digital converter comparator circuit includes a pair of differential amplifiers having their outputs normally intercoupled in a subtractive sense. At a sampling strobe time, the output of one differential amplifier is reversed such that outputs of the two differential amplifiers are additive. The period of time during which the output signals add can be made as short as desired, for example by successively operating differential coupling circuits at the amplifier outputs through an intervening delay line. A very small aperture time is secured which is substantially shorter than the time constant of subsequent circuitry. A latch circuit receives the output of the comparator for assuming one of two different states in accordance with the comparator sampled output.

Abstract: The invention provides an A/D converter which comprises reference voltage generator means for generating a plurality of reference input voltages from a power supply, a comparator composed of switching means for inputting into the A/D converter an external analog input voltage and the reference input voltages and of an amplifier for amplifying the respective input voltages, and control means for controlling the reference voltage generator means and the comparator on the basis of an output from the comparator; the amplifier circuit of the comparator sharing its power supply with the reference voltage generator means.

Abstract: An analog to digital converter used along with a variable resistive sensing means utilizes the capabilities of a microprocessor to charge and discharge a capacitor. The time required for this capacitor to discharge is dependent upon the value of the variable resistive sensing means. Circuitry is used to create a pulse whose pulse width is equal to the discharged time of a capacitor through the variable resistive sensing means.

Abstract: An improved MOS capacitor array formed on a semiconductor substrate comprises rectangular strips of an active region overlapped by rectangular strips of conductive material. The active region and conductive material are separated by an insulating layer. The strips form an array of capacitors which are more tightly packed than the prior art and which are less sensitive to alignment errors than the prior art.

Abstract: An improved differential voltage buffer amplifier circuit of the type having a pair of transistors connected in emitter-follower configuration with an input differential voltage signal applied between the bases thereof and a load resistor connected between the emitters thereof, which further includes a compensation circuit for eliminating a voltage transfer error resulting from current flow through the load, for thereby achieving a voltage gain value that is very close to one. The buffer circuit is particularly advantageous for use in a new high-accuracy A-D converter which is suitable for integrated circuit implementation.

Abstract: A serial data receiving circuit comprising a most significant bit input detecting circuit (20) for providing a given control signal in synchronism with input of the most significant bit of a serial data represented by twos complement and a data converter circuit (30B) for subjecting the serial data to a sign extension data when the control signal is active and providing the resultant sign extended data as a parallel data and shifting the serial data from a low order bit to a high order bit when the control signal is inactive and providing the shifted data as a parallel data.

Abstract: A phase compensation circuit for use with a resolver circuit that compensates for resolver angle measurement error without the use of special compensation windings on the resolver or the buffer amplifier associated with the compensation windings. With the present invention, primary windings from a plurality of resolvers may be reduction over conventional circuits. A digital computer is employed to process integrated data indicative of the phase shift of signals generated by the resolver, and compute error correction signals that compensate sine and cosine angle data output signals of the resolver. No resolver compensation windings are necessary and no additional electronic equipment is necessary. The present invention provides increased accuracy to fulfill more stringent angle measurement specifications.

Abstract: An adaptive analogue-to-digital converter arrangement comprises an analogue-to-digital converter (21) preceded by a variable-gain amplifier (4). In order to provide an accurate measure of the relative gain of the amplifier at each gain setting the output signal of an a.c. reference signal source (12) is frequency-multiplexed with the arrangement input signal applied to an input (1). After conversion to digital form by means of the A/D converter (21) the multiplexed signal is separated into its two components by means of filters (23,24), these being directed to respective bit fields (2A,2B) of an output (2), the reference component after amplitude detection (25).

Abstract: Analog-to-digital converter comprising a plurality of sigma-delta modulators, the input of the pulse shaper of a modulator always being coupled to the input of a next modulator via a coupling filter, and the output of the modulators being connected to the summing circuit via decimators, whereas in the decimators the filter function of the coupling filters is compensated. The loop filters in the modulators are described by third-order transfer functions with real poles and zeros.

Abstract: Sample values of a digital signal of a first sample rate are supplied to a digital filter for conversion into a digital signal of a second sample rate. The coefficients of the digital filter are calculated by a processor from the ratio of the sample rates or are obtained by a read-only memory containing sets of coefficients for respective sample rate ratios for which the apparatus is usable. Filtered sample values are read out of the digital filter at the desired second sample rate. A buffer memory is used at the input of the digital filter and a regulator is provided to prevent fluctuations in the filling of the buffer memory from emptying or exceeding the capacity of the buffer memory.

Abstract: Apparatus for testing data conversion/transfer functions in each of a plurality N of channels of a vibratory energy imaging system includes a multiplexer for providing, to an addressable memory having a plurality of L=2.sup.M locations in each of which a data word of B bits can be stored, a selected one of an input data word and a test data word, each of which can address one of the L locations of the memory means. The address multiplexer facilitates retrieval from memory of a B-bit data word having a value selected to implement a selected function for that channel, so that comparision of data from the selected test address with the data which has been sent to that location for storage, will indicate if proper data is stored for carrying out the designated function.

Abstract: An ac encoded signal to digital converter suitable for converting ac synchro or resolver signals to a corresponding digital angle value. A synchronous demodulator including a high pass input filter and low pass output filter utilizes the associated reference excitation signal to convert the individual ac encoded signals to corresponding dc values. The absolute value of the dc values are proportional to the amplitude of each of the respective ac encoded signals, but the dc value is negative if the ac encoded signal is 180.degree. out of phase with the reference excitation signal. These dc values are subsequently digitized and digitally processed based on their trigonometric relationship to extract the encoded angular position value.

Abstract: An analog-to-digital and digital-to-analog converter includes an array of capacitors each being differently weighed from the others, one electrode of each of the capacitors being connected to a common node. Switches are provided for selectively applying, in response to a first control signal, an analog input applied to an analog input terminal and a plurality of reference voltages to the other electrode of the capacitors. A comparator has a pair of input terminals whose inverting and non-inverting inputs are selectively switched over with respect to polarity in response to a second control signal. The comparator compares a voltage appearing on the node and applied to one of the input terminals and one of the reference voltages applied to the other input terminal. An analog output terminal is connected to the output of the comparator. A successive comparison register sequentially takes in outputs of the comparator in response to a third control signal.

Abstract: A dynamic brake control system for an alternating current motor powered by a variable voltage, variable frequency inverter which regulates the speed of the motor. An AC to DC converter converts AC line power to DC power with the DC power being transferred to the inverter via a DC link. During electrical dynamic braking, the inverter functions to transfer power from the motor to the DC link. The torque available to the motor during braking is a function of the receptivity of the DC link. Link receptivity controlled by a resistance connected to the link in which the resistance is modulated at a frequency dependent upon the incoming AC line frequency at the converter. The modulation is binarily controlled so as to minimize ripple current on the DC link without the necessity of providing high frequency control of the modulating electronics.