Patents Examined by Benjamin Tzu-Hung Liu
  • Patent number: 11227982
    Abstract: An LED package creates a narrow beam in a very compact package without use of a lens. A plastic is molded around a metal lead frame (12, 14) to form a molded cup (26), where the cup has parabolic walls extending from a bottom area of the cup to a top thereof. The lead frame forms a first set of electrodes exposed at the bottom area of the cup for electrically contacting a set of LED die electrodes (18, 20). The lead frame also forms a second set of electrodes outside of the cup for connection to a power supply. A reflective metal (28) is then deposited on the curved walls of the cup. An LED die (16) is mounted at the bottom area of the cup and electrically connected to the first set of electrodes. The cup is then partially filled with an encapsulant (64) containing a phosphor (66).
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: January 18, 2022
    Assignee: Lumileds LLC
    Inventor: Mark Melvin Butterworth
  • Patent number: 11222842
    Abstract: A method and structure for forming a local interconnect, without routing the local interconnect through an overlying metal layer. In various embodiments, a first dielectric layer is formed over a gate stack of at least one device and a second dielectric layer is formed over a contact metal layer of the at least one device. In various embodiments, a selective etching process is performed to remove the second dielectric layer and expose the contact metal layer, without substantial removal of the first dielectric layer. In some examples, a metal VIA layer is deposited over the at least one device. The metal VIA layer contacts the contact metal layer and provides a local interconnect structure. In some embodiments, a multi-level interconnect network overlying the local interconnect structure is formed.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 11, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Wen Chang, Yi-Hsiung Lin
  • Patent number: 11217721
    Abstract: Provided is a light-emitting device that includes a first electrode layer, a first conduction type layer, a second conduction type layer, an active layer, and a second electrode layer. The first conduction type layer includes a current injection region formed by the first electrode layer and a current non-injection region. A waveguide structure included in the first conduction type layer, the active layer, and the second conduction type layer includes a first region and a second region. The first region has a first waveguide that is the current injection region and the current non-injection region and has a first refractive index difference. The second region has a second waveguide arranged to be extended from the first waveguide to the first end and has a second refractive index difference greater than the first refractive index difference. The second waveguide has a region narrowing toward the first end.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 4, 2022
    Assignee: SONY CORPORATION
    Inventors: Kentaro Fujii, Tomoki Ono, Yoshiaki Watanabe
  • Patent number: 11208320
    Abstract: A MEMS microphone includes a substrate defining a cavity including a first sidewall extending a vertical direction, a back plate disposed over the substrate and defining a plurality of acoustic holes, a diaphragm disposed between the substrate and the back plate, the diaphragm having at least one vent hole, an anchor extending from a circumference of the diaphragm to connect an end portion of the diaphragm to an upper surface of the substrate, and at least one path member communicating with the vent hole, the path member providing a flow path for the acoustic pressure to flow downwardly toward the cavity.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: December 28, 2021
    Assignee: DB HITEK CO., LTD.
    Inventors: Dae Young Kim, Jin Hyung Lee
  • Patent number: 11211564
    Abstract: An organic light-emitting device having low-driving voltage, improved efficiency, and long lifespan includes: a first electrode; a second electrode facing the first electrode; a first layer between the first electrode and the second electrode, the first layer including a first compound; a second layer between the first layer and the second electrode, the second layer including a second compound; and a third layer between the second layer and the second electrode, the third layer including a third compound; wherein the first compound does not include a nitrogen-containing heterocyclic group comprising *?N—*? as a ring forming moiety, and wherein the first compound, the second compound, and the third compound each independently include at least one group selected from groups represented by Formulae A to C:
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: December 28, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seulong Kim, Younsun Kim, Dongwoo Shin, Jungsub Lee, Naoyuki Ito, Jino Lim
  • Patent number: 11211583
    Abstract: The encapsulation structure includes a first barrier layer and a second barrier layer, and the first barrier layer is located between an object to be encapsulated and the second barrier layer. The display panel includes the encapsulation structure mentioned in the above technical solution. The display apparatus includes the display panel mentioned in the above technical solution.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: December 28, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Dawei Wang, Youwei Wang
  • Patent number: 11195778
    Abstract: An electronic power module, including at least one semiconductor component, which is arranged on a support, as well as a cooling element, which is in thermal contact with the semiconductor component, wherein the support includes a semiconductor material and, at the same time, serves as a cooling element.
    Type: Grant
    Filed: November 24, 2016
    Date of Patent: December 7, 2021
    Assignees: AUDI AG, ABB Schweiz AG
    Inventors: Andreas Apelsmeier, Günter Vetter
  • Patent number: 11183670
    Abstract: An organic light emitting diode (OLED) device includes an emissive layer having a first sublayer with a first emitter as a dopant, a second sublayer with a second emitter as a dopant, and a third sublayer with a third emitter as a dopant. The second sublayer is between the first sublayer and the third sublayer. A concentration of the first emitter in the first sublayer exceeds a concentration of the third emitter in the third sublayer, and the concentration of the third emitter in the third sublayer exceeds a concentration of the second emitter in the second sublayer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: November 23, 2021
    Assignee: Arizona Board of Regents on behalf of Arizona State University
    Inventors: Jian Li, Kody George Klimes
  • Patent number: 11177438
    Abstract: An example method includes: forming a bottom electrode on a substrate and forming a patterned mask layer on the bottom electrode; thermal oxidizing the bottom electrode layer via the patterned mask layer by applying a thermal process and a first plasma; removing a gaseous status of the bottom electrode oxide using a first vacuum purge; removing a solid status of the bottom electrode oxide by applying a second plasma; removing the gaseous status and the solid status of the bottom electrode oxide using a second vacuum purge to form a patterned bottom electrode; removing the patterned mask layer; forming a filament forming layer on the patterned bottom electrode; and a top electrode on the filament forming layer. The filament forming layer is configured to form a filament within the filament forming layer responsive to a switching voltage being applied to the filament forming layer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 16, 2021
    Assignee: Tetramen Inc.
    Inventors: Minxian Zhang, Ning Ge
  • Patent number: 11177273
    Abstract: A nonvolatile memory device includes a substrate; a memory cell array formed on the substrate in a vertically stacked structure; and a row decoder configured to supply a row line voltage to the memory cell array, the row decoder including a plurality of pass transistors. The row line voltage is supplied through a plurality of row lines connecting the pass transistors to the memory cell array. Each of the row lines includes a wiring line parallel with a main surface of the substrate and a contact perpendicular to the main surface of the substrate. The wiring line of at least one row line among the row lines includes a plurality of conductive lines.
    Type: Grant
    Filed: June 3, 2018
    Date of Patent: November 16, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Bum Kim, Sung-Hoon Kim
  • Patent number: 11150495
    Abstract: A technique is described to deterministically tune the emission frequency of individual semiconductor photon sources, for example quantum dots. A focused laser is directed at a film of material that changes form when heated (for example, a phase change material that undergoes change between crystal and amorphous forms) overlaid on a photonic membrane that includes the photon sources. The laser causes a localized change in form in the film, resulting in a change in emission frequency of a photon source.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: October 19, 2021
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Joel Q. Grim, Allan S. Bracker, Samuel Carter, Daniel Gammon
  • Patent number: 11139142
    Abstract: A plurality of energy filter values are obtained using a model that simulates potential distribution within a 3D feature when an electron beam of an SEM impinges on a selected area that includes the 3D feature. A correspondence is extracted between the plurality of energy filter values and respective depths of the 3D feature along a longitudinal direction by analyzing the simulated potential distribution. A plurality of SEM images of the 3D feature corresponding to the plurality of energy filter values are obtained. The plurality of SEM images are associated with their respective depths based on the extracted correspondence between the plurality of energy filter values and the respective depths. A composite 3D profile of the 3D feature is generated from the plurality of SEM images obtained from various depths of the 3D feature.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 5, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Ofer Yuli, Samer Banna
  • Patent number: 11133216
    Abstract: A nitridation treatment method is provided. The nitridation treatment method includes executing a nitridation treatment with respect to a hydrophobic surface defining an interconnect trench to convert the hydrophobic surface to a hydrophilic surface. The nitridation treatment method further includes depositing a seed layer including a conductive material and manganese on the hydrophilic surface. The nitridation treatment method also includes thermally driving all the manganese out of the seed layer to form a diffusion barrier including manganese at the hydrophilic surface. In addition, the nitridation treatment method includes filling remaining space in the interconnect trench with the conductive material to form an interconnect.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, Roger A. Quon, Chih-Chao Yang
  • Patent number: 11133261
    Abstract: An electronic device may be a first package. The first package may include a first substrate having a first mounting surface. A first die may be coupled to the first mounting surface. A first interconnect region may be laterally spaced from the first die. The first package may be interconnected with a second package. The second package may include a second die coupled to a second mounting surface. Interconnection of the first package with the second package may establish one or more electrical communication pathways between the first package and the second package. The interconnection of the first package with the second package may interconnect the first die with the second die such that the first die and second die are in communication only through the one or more electrical communication pathways.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Chee Kheong Yoon, Jia Yan Go
  • Patent number: 11133189
    Abstract: The present disclosure relates to methods and apparatuses related to the deposition of a protective layer selective to an interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In some embodiments, a method comprises: forming an interlayer dielectric layer on a substrate; covering a trench region with a metal liner, wherein the trench region is situated above the substrate and formed within the interlayer dielectric layer; and depositing a protective layer selective to the interlayer dielectric layer so that the protective layer is formed onto a top portion associated with the interlayer dielectric layer. In various embodiments, the depositing the protective layer comprises: repeatedly depositing the protective layer via a multi-deposition sequence; or depositing a self-assembled monolayer onto the top portion.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 28, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kisup Chung, Ekmini Anuja De Silva, Andrew Greene, Siva Kanakasabapathy, Indira Seshadri
  • Patent number: 11127738
    Abstract: A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: September 21, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, David Edward Fisch, Kenneth Duong, Xu Chang, Liang Wang
  • Patent number: 11127846
    Abstract: A HEMT device includes a gate electrode disposed on a semiconductor layer; a first dielectric layer disposed on the gate electrode and having a first recess on a first side of the gate electrode, wherein a bottom surface of the first recess is lower than a top surface of the gate electrode; a source field plate disposed on the first dielectric layer and extending from a second side of the gate electrode into the first recess; a second dielectric layer disposed on the source field plate; a source electrode disposed on the second dielectric layer and electrically connected to the source field plate; a third dielectric layer disposed on the source electrode; and a drain structure disposed on the first side of the gate electrode and passing through the third dielectric layer, wherein the first recess is located between the drain structure and the gate structure.
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: September 21, 2021
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventor: Chih-Yen Chen
  • Patent number: 11127743
    Abstract: A transistor including a carrier transit layer that includes a compound semiconductor and a carrier supply layer in contact with the carrier transit layer. The carrier supply layer includes a compound semiconductor of a different type from the carrier transit layer. The transistor includes a gate electrode provided on the carrier supply layer, and a source electrode and a drain electrode provided on another surface of the carrier transit layer that is opposite to one surface on which the carrier supply layer is provided.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: September 21, 2021
    Assignee: SONY CORPORATION
    Inventors: Shigeru Kanematsu, Katsuhiko Takeuchi, Masashi Yanagita, Shinichi Wada
  • Patent number: 11121334
    Abstract: A field effect transistor having a channel that comprises three-dimensional graphene foam. The subject matter of the invention concerns a three dimensional field-effect transistor having a channel based on graphene foam and the use of ionic liquid as a gate. The graphene foam is made of a three-dimensional network of single and double layer graphene that extends in all the three dimensions. Metal contacts on either end of the graphene foam form the drain and source contacts of the transistor.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: September 14, 2021
    Assignee: Trustees of Tufts College
    Inventors: Sameer Sonkusale, Shideh Kabiri Ameri Abootorabi, Pramod Kumar Singh
  • Patent number: 11114562
    Abstract: A semiconductor device includes: a first gate structure on a substrate; a first drain region having a first conductive type adjacent to one side of the first gate structure; a source region having the first conductive type adjacent to another side of the first gate structure; and a first body implant region having a second conductive type under part of the first gate structure.
    Type: Grant
    Filed: February 8, 2018
    Date of Patent: September 7, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Chia-Huei Lin, Kuo-Yuh Yang