Abstract: Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented.

Abstract: Vertical field effect transistors (VFETs) having a gradient threshold voltage and an engineered channel are provided. The engineered channel includes a vertical dog-bone shaped channel structure that is composed of silicon having a germanium content that is 1 atomic percent or less and having a lower portion having a first channel width, a middle portion having a second channel width that is less than the first channel width, and an upper portion having the first channel width. Due to the quantum confinement effect, the middle portion of the vertical dog-bone shaped channel structure has a higher threshold voltage than the lower portion and the upper portion of the vertical dog-bone shaped channel structure. Hence, the at least one vertical dog-bone shaped channel structure has an asymmetric threshold voltage profile. Also, the VFET containing the vertical dog-bone shaped channel structure has improved electrical characteristics and device performance.

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.

Abstract: In an example, a method may include closing an opening in a structure with a sacrificial material at a first processing tool, moving the structure from the first processing tool to a second processing tool while the opening is closed, and removing the sacrificial material at the second processing tool. The structure may be used in semiconductor devices, such as memory devices.

Abstract: A Magnetic Tunnel Junction (MTJ) device can include a second Precessional Spin Current (PSC) magnetic layer of Ruthenium (Re) having a predetermined thickness and a predetermined smoothness. An etching process for smoothing the PSC magnetic layer can be performed in-situ with various deposition processes after a high temperature annealing of the MTJ formation.

Abstract: The present disclosure is directed to a leadframe package with a surface mounted semiconductor die coupled to leads of the leadframe package through wire bonding. The leads are partially exposed outside the package and configured to couple to another structure, like a printed circuit board (PCB). The exposed portions, namely outer segments, of the leads include a plating or coating layer of a material that enhances the solder wettability of the leads to the PCB through solder bonding. The enclosed portions, namely inner segments, of the leads do not include the plating layer of the outer segment and, thus, include a different surface material or surface finish.

Abstract: A semiconductor device may include a first semiconductor chip, a second semiconductor chip, an encapsulant encapsulating the first and second semiconductor chips, a first signal terminal extending over inside and outside of the encapsulant and connected to the first semiconductor chip inside the encapsulant, and a second signal terminal extending over the inside and the outside of the encapsulant and connected to the second semiconductor chip inside the encapsulant. The first and second signal terminals may protrude from the encapsulant in a same direction. The first signal terminal may include, inside the encapsulant, a section where the first signal terminal extends farther away from the second signal terminal along a direction toward the first semiconductor chip. The second signal terminal may include, inside the encapsulant, a section where the second signal terminal extends farther away from the first signal terminal along a direction toward the second semiconductor chip.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a gate structure formed over the substrate. The semiconductor structure further includes a first source/drain structure and a second source/drain structure formed in the substrate adjacent to the gate structure. The semiconductor structure further includes an interlayer dielectric layer formed over the substrate to cover the gate structure, the first source/drain structure, and the second source/drain structure. The semiconductor structure further includes a first conductive structure formed in the interlayer dielectric layer over the first source/drain structure. The semiconductor structure further includes a second conductive structure formed in the interlayer dielectric layer over the second source/drain structure.

Abstract: A method includes forming a wide band gap (WBG) epitaxial layer on an engineered substrate. The WBG epitaxial layer includes a plurality of groups of epitaxial layers. The engineered substrate includes engineered layers formed on a bulk material having a coefficient of thermal expansion (CTE) matching a CTE of the WBG epitaxial layer. The method also includes forming a plurality of WBG devices based on the plurality of groups of epitaxial layers by: for each respective WBG device, forming internal interconnects and electrodes within a respective group of epitaxial layers. The method further includes forming external interconnects between the electrodes of different WBG devices of the plurality of WBG devices to form an integrated circuit.

Abstract: A structure with micro device including a substrate, at least one micro device and at least one holding structure is provided. The micro device is disposed on the substrate and has a top surface away from the substrate, a bottom surface opposite to the top surface, and a circumferential surface connecting the top surface and the bottom surface. The holding structure is disposed on the substrate. From the cross-sectional view, a thickness of the holding structure is not fixed from the boundary of the top surface and the circumferential surface to the substrate. The micro device is connected to the substrate through the holding structure.

Abstract: A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

Abstract: A device includes an integrated circuit including a single standard cell that is selected from a standard cell library used for design of the layout of the integrated circuit. The single standard cell includes a first active region, a second active region, a first gate, a second gate, and a third gate. The first gate is arranged over the first active region, for formation of at least one first electrostatic discharge (ESD) protection component. The second gate is separate from the first gate, and the second gate is arranged over the second active region, for formation of at least one second ESD protection component. The third gate is separate from the first gate and the second gate, and the third gate is arranged over the first active region and the second active region, for formation of at least one transistor.

Abstract: A chip-scale packaging process for wafer-level camera manufacture includes aligning an optics component wafer with an interposer wafer having a photoresist pattern that forms a plurality of transparent regions, bonding the aligned optics component wafer to the interposer wafer, and dicing the bonded optics component wafer and interposer wafer such that each optics component with interposer has a transparent region. The process further includes dicing an image sensor wafer, aligning the pixel array of each image sensor with the transparent region of a respective optics component with interposer, and bonding each image sensor to its respective optics component with interposer. Each interposer provides alignment between its respective optics component center and its respective pixel array center of the image sensor based on the respective transparent region. The interposer further provides a back focal length for focusing light from the optics component onto a top surface of the pixel array.

Abstract: Systems and methods for determining a model for predictive inference on an operation of a machine. A processor is configured to acquire time series data, the times series data includes training data and test data, the time series data represents an operation of the machine for a period of time, and the training data includes observations labeled with an outcome of the predictive inference. Apply recursive and stable filters for filtering at a training time, at a test time or both, such that a data point in the filtered time series data corresponds to an observation in the time series data that is a function of the corresponding observation and past observations in the time series data preceding the corresponding observation. Determine the model for the predictive inference using the training data, based on filtering the training data with filters to produce filtered time series data, and store in memory.

Abstract: A perpendicular synthetic antiferromagnetic (pSAF) structure and method of making such a structure is disclosed. The pSAF structure comprises a first high perpendicular Magnetic Anisotropy (PMA) multilayer and a second high PMA layer separated by a thin Ruthenium layer. Each PMA layer is comprised of a first cobalt layer and a second cobalt layer separated by a nickel/cobalt multilayer. After each of the first and second PMA layers and the Ruthenium exchange coupling layer are deposited, the resulting structure goes through a high temperature annealing step, which results in each of the first and second PMA layers having a perpendicular magnetic anisotropy.

Abstract: Thermal management technology is disclosed. A thermal management component in accordance with the present disclosure can comprise a heat spreader having a plurality of microchannels. The thermal management component can also comprise a plurality of fins directly coupled to the heat spreader to provide surface area for heat transfer. In another aspect, a thermal management component can comprise a heat spreader having a plurality of microchannels, and an inlet port and an outlet port in fluid communication with the plurality of microchannels. The thermal management component can also comprise a plurality of fins coupled to the heat spreader to provide surface area for heat transfer. Additionally, the thermal management component can comprise a fluid conduit thermally coupled to the plurality of fins and fluidly coupled to the outlet port and the inlet port to facilitate flow of a heat transfer fluid through the microchannels and the fluid conduit.

Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.

Abstract: Disclosed is an LED package, an LED module and a method for manufacturing the LED package. The LED package includes a lead frame comprising an insulating substrate and a plurality of first pins to a plurality of fourth pins formed on the insulating substrate, a plurality of first bonding pads to a plurality of fourth bonding pads, and a plurality of first wires to a plurality of fourth wires; a plurality of pixel units, each of which includes a first LED element, a second LED element and a third LED element; and an encapsulating composition covering the lead frame and allowing light to transmit. The LED package includes the plurality of LED elements of pixel units and implements internal interconnection with additional wires, thereby reducing the number of bonding pads of the LED package, and thus the manufacturing cost is reduced and the product reliability is improved.

Abstract: Disclosed is a cooling assembly for circuit boards. In one embodiment, the assembly includes a circuit board that is thermally and physically coupled to a heat spreader by a thermal interface. In one configuration, the circuit board is formed from a semiconductor material and includes a first board surface on which integrated circuits are mounted and a second board surface opposite the first board surface. The heat spreader is formed from a thermally conductive material and includes a plurality of vanes that are spaced apart from one another. The thermal interface is coupled between at least one area of the second board surface of the circuit board and a contact area of each of the plurality of vanes. Heat generated by the integrated circuits is conducted from at least one integrated circuit to the plurality of vanes of the heat spreader through the circuit board and the thermal interface.

Abstract: A method of forming a fin field effect transistor circuit is provided. The method includes forming a plurality of vertical fins on a substrate, and forming a protective liner having a varying thickness on the substrate and plurality of vertical fins. The method further includes removing thinner portions of the protective liner from the substrate to form protective liner segments on the plurality of vertical fins. The method further includes removing portions of the substrate exposed by removing the thinner portions of the protective liner to form trenches adjacent to at least one pair of vertical fins and two substrate mesas. The method further includes laterally etching the substrate mesa to widen the trench, reduce the width of the substrate mesa to form a supporting pillar, and undercut the at least one pair of vertical fins, and forming a first bottom source/drain layer in the widened trench.