Abstract: A method including obtaining a selected component of optical aberration of or for a lithography apparatus, under a processing condition; computing an approximate of a cost function, based on the selected component; and producing an adjustment of the lithography apparatus or a patterning process that uses the lithography apparatus, based on the approximate of the cost function.

Abstract: A method is presented for layout decomposition including creating a first graph representative of an integrated circuit layout to be multiple-patterned, when a computer is invoked to decompose the layout, and decomposing each of a first subset of a multitude of sub-graphs into at least three sets when a valid coloring solution is returned for the layout. The multitude of sub-graphs is created from the first graph by dividing the first graph. The method further includes approximately decomposing each of the first subset into at least three sets using a hybrid evolutionary algorithm when the hybrid evolutionary algorithm does not return a valid coloring solution for the layout, and forming a colored graph representative of the layout by merging the at least three sets to generate one of at least three colors for each one of a multitude of vertices of the first graph.

Abstract: The efficiency of electronic design automation is increased by building, as an electronic data structure, a timing graph characterizing a putative integrated circuit design; identifying at least one of an edge and a node in the timing graph that requires canonical timing adjustment; and electronically calculating a deterministic timing adjustment for each of a plurality of corner cases. Based on the calculated deterministic timing adjustment for each of the plurality of corner cases, the canonical timing adjustment is determined for the at least one of an edge and a node; the canonical timing adjustment is applied to the timing graph; and the timing graph is updated based on the application of the canonical timing adjustment.

Abstract: A search engine receives data describing reference geometry and generates a hash based on the reference geometry. A reference bloom filter is generated for the reference geometry based on the hash. The search engine performs a search to determine whether instances of the reference geometry are present in an integrated circuit (IC) layout. The search includes comparing the reference bloom filter with each one of a plurality of bloom filters corresponding to a plurality of subdomains of the IC layout. Based on results of the comparison, one or more subdomains of interest are identified and searched to determine whether the particular reference geometry is present in the subdomain.

Abstract: Disclosed is a method of generating a physical unclonable function (PUF) by causing unpredictable partial process failure for a semiconductor process. In a designing process, a second mask pattern may be printed by distorting a size and/or shape of at least one mask window included in a designed first mask pattern, without violating semiconductor design rules. A PUF may be generated using a photomask including the printed second mask pattern for photolithography.

Abstract: The following relates generally to analog circuit re-design. Some embodiments identify a candidate component of the circuit by determining that if the candidate component is adjusted or replaced, the circuit will satisfy a requirement metric. In some implementations, an optimization problem or Bayesian reasoning may be used to change parameters of the candidate component to create a replacement component. In some implementations, a replacement component of a different type than the candidate component may be selected by solving a mixed-integer optimization program or by using a non-linear program with continuous parameters.

Abstract: A depleted EV transmits first information including a current location of the depleted EV to a server. Each of the other vehicles transmits second information including a current location of the vehicle to the server. When the server receives from the depleted EV a help signal requesting power supply from another vehicle to the depleted EV, the server selects, from among the other vehicles, a rescue EV to supply electric power to the depleted EV, using the first information and the second information.

Abstract: Each vehicle includes a detection device configured to detect a situation outside the vehicle. When a server receives from a depleted EV a help signal requesting power supply from another vehicle to the depleted EV, the server selects, from among the other vehicles, a rescue EV to supply electric power to the depleted EV. The rescue EV moves to the depleted EV, determines a stopping position of the rescue EV from a situation around the depleted EV detected by the detection device, and performs power supply to the depleted EV at the stopping position.

Abstract: Each vehicle includes a detection device configured to detect a situation outside the vehicle. When a server receives from a depleted EV a help signal requesting power supply from another vehicle to the depleted EV, the server selects, from among the other vehicles, a rescue EV to supply electric power to the depleted EV. The rescue EV moves to the depleted EV, stops behind the depleted EV detected by the detection device, and supplies power to the depleted EV while being stopped behind the depleted EV.

Abstract: Disclosed are devices, apparatuses, systems, computer readable media, and methods for improving the security of circuitry designs using HDL code. In one aspect a method is disclosed. the method includes receiving a hardware design language (HDL) representation of a circuit; inserting flow tracking into the HDL representation, wherein the flow tracking adds one or more security labels that are tracked throughout the circuit; and generating an enhanced HDL representation of the circuit, wherein the enhanced HDL representation comprises the HDL representation and the flow tracking, wherein the enhanced representation including the one or more security labels that are tracked throughout the circuit enables a security determination a model for tracking timing-based information flows through HDL code is disclosed. The disclosed technology is used to verify security properties on a variety of equipment including crypto cores, bus architectures, caches and arithmetic modules.

Abstract: Electronic design automation systems, methods, and media are presented for cell cloning during circuit design. In one embodiment, for a circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree, a delay is identified for each flip-flop element. The flip-flop elements are clustered by delay to generate at least two clusters of flip-flop elements. Elements within the clusters are then grouped by physical characteristics to generate delay groups of flip-flop elements. An updated routing tree is then generated for the circuit design using the first delay group and the second delay group.

Abstract: A detection circuit and an electronic device using the detection circuit are provided. The detection circuit includes a fourth branch, a fifth branch and a third energy storage unit. The fourth branch includes multiple fourth switches, and the fifth branch includes multiple fifth switches. A preset electrical signal threshold is sampled and applied to the third energy storage unit by controlling the multiple fourth switches in the fourth branch, and a voltage difference between two detection terminals of a first energy storage unit is sampled and applied to the third energy storage unit by controlling the multiple fifth switches in the fifth branch, to compare the voltage difference between the two detection terminals with the preset electrical signal threshold.

Abstract: The present disclosure relates to a method for use in a formal verification of an electronic design. Embodiments may include receiving, using a processor, a reference model including a software specification and an implementation model at a register transfer level. Embodiments may also include generating one or more invariants based upon, at least in part, the reference model, wherein generating one or more invariants includes applying a semantic analysis. Embodiments may further include automatically generating at least one case splitting candidate based upon, at least in part, the one or more generated invariants.

Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spatially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spatially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.

Abstract: A method for supplying a number of electric charging stations with electricity, wherein AC voltage provided by an electricity source is transformed into a prescribed AC voltage level by at least one transformer via at least one star winding and at least one delta winding and subsequently routed via AC voltage lines to the number of electric charging stations and converted directly to direct current in respective charging stations from the number of electric charging stations locally by at least two rectifiers of the charging stations.

Abstract: A process method for producing a photomask with double patterns. The processing method includes obtaining a contact distribution pattern, having multiple contacts. The contacts are sorted into multiple contact blocks in array type, pair type and isolation type. The contacts are decomposed into a first patterning group and a second patterning group, which are configured to interpose to each other. The numbers of contacts of the first patterning group and the second patterning group are equal within an error range. The first patterning group and the second patterning group are check whether or not having adjacent two contacts with a distance less than a minimum distance. If it is less than a minimum distance, one of the adjacent two contacts is changed from a current one of the first patterning group and the second patterning group to another. The first/second patterning groups are output to from first/second photomasks.

Abstract: The present disclosure provides a built-in robotic floor cleaning system installed within the infrastructure of a workspace and a method for controlling and integrating such system in a workspace. The built-in robotic floor cleaning system comprises a robotic floor cleaning device and a docking station for charging the robotic floor cleaning device wherein the docking station is built into the infrastructure of the workspace. The system may further comprise a control panel integrated into the infrastructure of the workspace to deliver inputs from users and display outputs from the system. The system may further comprise a variety of types of confinement methods built into the infrastructure of the workspace to aid the robotic floor cleaning device in navigation. The system may also be provided with a virtual map of the environment during an initial set-up phase to assist with navigation.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: Various embodiments provide for analyzing (e.g., debugging) waveform data generated for a simulated circuit design, which can be used as part of electronic design automation (EDA). For example, where a user modifies a circuit design in a manner that impacts a next simulation run performed on the circuit design, various embodiments perform the next simulation run only on one or more portions of the circuit design affected by the user's modifications, while the results/simulated values for the rest of the circuit design are kept or reused.

Abstract: A device is disclosed that includes a cell block, at least one first metal interconnect, and second metal interconnects. The cell block includes a pin disposed at a Nth metal layer in a cell layout. The at least one first metal interconnect is disposed at a (N+1)th metal layer above the Nth metal layer and stacked over the pin, and electrically coupled to the pin. The second interconnects are disposed at a (N+2)th metal layer and stacked over the at least one first metal interconnect, and parallel to each other. The second metal interconnects are electrically coupled to the at least one first metal interconnect, and forming an equivalent tapping point of the pin of the cell block. The equivalent tapping point and the pin are vertically overlapped with each other, and fabrication of the device is initiated after a DRC or a SEM simulation test is passed.