Abstract: A method of designing an integrated circuit includes receiving input data defining the integrated circuit, receiving information from a standard cell library including a plurality of standard cells, receiving information from a modified cell library including at least one modified cell having a same function as a corresponding standard cell among the plurality of standard cells and having a higher routability than the corresponding standard cell and generating output data by performing placement and routing in response to the input data, the information from the standard cell library and the information from the modified cell library.

Abstract: Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.

Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: A broadband Green's function computation technique that employs low wavenumber extraction on a modal summation is used to model the waveguide behavior of electronic components, systems, and interconnects on a printed circuit board. Use of the broadband technique permits discretizing the surface of the printed circuit board across a wide range of frequencies all at once. The broadband Green's function is also extended to via waveguides on circuit boards and power/ground plane waveguides of arbitrary shape. Such a method can analyze a given circuit board geometry over a broad frequency range several hundred times faster than is otherwise possible with existing commercial analysis tools. The present method is useful in electronic design automation for analyzing signal integrity and power integrity, reducing electromagnetic interference and ensuring electromagnetic compatibility.

Abstract: Systems and methods of performing boundary assertion-based power recovery in integrated circuit design set boundary assertions based on a specified slack value. A boundary defines a set of components of the integrated circuit and setting the boundary assertions includes specifying arrival times at input pins of the set of components and required arrival times at output pins of the set of components. The method includes performing timing analysis of the set of components and performing the power recovery by replacing ones of the set of components based on a result of the timing analysis. The integrated circuit design is provided for fabrication based on completing the power recovery.

Abstract: An etching effect prediction method includes determining a sample area of a mask pattern in which etch bias is to be predicted, determining input parameters indicating physical characteristics affecting an etching process undertaken in the sample area, comparing an output value obtained by inputting the input parameters to an artificial neural network, to a measured value of the etch bias that occurred in the sample area, and operating the artificial neural network until a difference between the output value and the measured value is equal to or less than a predetermined reference value.

Abstract: A method including modeling high resolution patterning error information of a patterning process involving a patterning device in a patterning system using an error mathematical model, modeling a correction of the patterning error that can be made by a patterning device modification tool using a correction mathematical model, the correction mathematical model having substantially the same resolution as the error mathematical model, and determining modification information for modifying the patterning device using the patterning device modification tool by applying the correction mathematical model to the patterning error information modeled by the error mathematical model.

Abstract: Various techniques implement an electronic design with physical simulations using layout artwork. The approximate behaviors of the electronic design are determined. A region in the electronic design is identified. A first three-dimensional model is identified, if pre-existing, or generated, if non-existing, for the region in the electronic design. The behaviors of the region is determined using at least physics-based techniques or methodologies that are preconditioned upon at least a portion of the approximate behaviors determined for the electronic design.

Abstract: A processor synthesis device inserts a stop circuit into a circuit configuration, which is defined by processor model information and includes a plurality of operators, based on instruction set information that defines an instruction set including a plurality of instructions, the stop circuit stopping an operator not used in an instruction to be executed among the plurality of operators when each of the plurality of instructions is executed. The processor synthesis device generates processor synthesis information which is an RTL description defining a circuit configuration into which the stop circuit is inserted.

Abstract: A lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate. A functional relationship between local height deviations across a substrate and focus information, such as a determined focus amount, is determined for a substrate, e.g., a reference substrate. Height deviations are subsequently measured for another substrate, e.g. a production substrate. The height deviations for the subsequent substrate and the functional relationship are used to determine predicted focus information for the subsequent substrate. The predicted focus information is then used to control the lithographic apparatus to apply a product pattern to the product substrate.

Abstract: Various examples of a technique for performing optical proximity correction and for forming a photomask are provided herein. In some examples, a layout is received that includes a shape to be formed on a photomask. A plurality of target lithographic contours are determined for the shape that includes a first target contour for a first set of process conditions and a second target contour that is different from the first target contour for a second set of process conditions. A lithographic simulation of the layout is performed to produce a first simulated contour at the first set of process conditions and a second simulated contour at the second set of process conditions. A modification to the layout is determined based on edge placement errors between the first simulated contour and the first target contour and between the second simulated contour and the second target contour.

Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.

Abstract: The generation of reversible circuits from high-level code is desirable in a variety of application domains, including low-power electronics and quantum computing. However, little effort has been spent on verifying the correctness of the results, an issue of particular importance in quantum computing where such circuits are run on all inputs simultaneously. Disclosed herein are example reversible circuit compilers as well as tools and techniques for verifying the compilers. Example compilers disclosed herein compile a high-level language into combinational reversible circuits having a reduced number of ancillary bits (ancilla bits) and further having provably clean temporary values.

Abstract: A power control method and an electronic device and/or connecting unit to implement the power control method is provided. The electronic device includes a first interface unit configured to be connected to an external device that can receive and provide power to the electronic device, a second interface unit configured to be connected to an external charger that can provide power for the external device and the electronic device, and a main controller configured to detect whether or not the external charger is connected, and receive and direct power from the external device or the external charger according to whether or not the external charger is connected.

Abstract: One or more properties can be associated with a design object in a microdevice design. The design object may be an object in a physical layout design for a microdevice, such as a geometric element in a layout design. The design object also may be a collection of geometric elements in a layout design, such as a net, a cell in a hierarchical design, or even a collection of all of the geometric elements in a layer of a design. Still further, the design object may even be an item in a logical circuit design, such as a net in a logical circuit design for an integrated circuit. The values of one or more properties may be statically assigned for or dynamically generated during a design process performed by an electronic design automation tool. A property may be assigned a constant value or a value defined by an equation or other type of script that includes one or more variables. A property may be simple, where the definition of the property's value is not dependent upon the value of any other properties.

Abstract: Exemplary embodiments of the present disclosure can include an exemplary system, method and computer-accessible medium for camouflaging a design of an integrated circuit(s) (IC), can include, for example, receiving information related to a plurality of input combinations to the ICs, and camouflaging the design of the ICs by limiting a discriminating ability of the input combination to a predetermined constant number of incorrect assignments. An incorrect output can be intentionally produced for a predetermined constant number of secret minterms of the ICs. An output of the ICs can be restored for the secret minterms using a CamoFix block. The CamoFix block can include a CamoInputMapping block(s), a CamoSecGen block(s) or a comparator block(s).

Abstract: A method for designing a system on a target device includes generating a first netlist for a first version of the system after performing synthesis in a first compilation. Optimizations are performed on the first version of the system during placement and routing in the first compilation resulting in a second netlist. A third netlist is generated for a second version of the system after performing synthesis in a second compilation. A hybrid netlist is generated from the first, second, and third netlists. Incremental placement and routing are performed on portions of the hybrid netlist that are new to the first compilation.

Abstract: A two-dimensional representation of a polygon is converted to a parametric representation. A smoothing filter is applied to the parametric representation to produce corner rounding. In some embodiments, a polygon layout plus a model that specifies how much corner rounding should be applied are taken as inputs. The desired amount of rounding to the corners in the input polygons is applied and this produces a new polygon layout with corners that are properly rounded as its output. The process can be implemented so that it does not induce any pattern-size dependent bias. It also can be designed so that it does not induce line-end pullbacks. However, this feature can be turned off if line-end pullbacks are deemed appropriate for the specific application.

Abstract: Various techniques implement an electronic design with hybrid analysis techniques. An activity map is identified or generated for an electronic design. The electronic design is reduced into a reduced electronic design at least by applying a plurality of reduction processes to different portions of the electronic design based in part or in whole upon the activity map. Transient behaviors of the electronic design may be determined or predicted at least by performing one or more transient analyses on a representation of the electronic design with a simulation start point based in part or in whole upon the activity map. The electronic design may then be implemented for manufacturing at least by modifying or correcting the electronic design based at least in part upon the transient behaviors.

Abstract: A charging connection device for a motor vehicle, at least one electromotor designed for driving the motor vehicle, including a charging cable, at its first end with a power supply plug for a household power supply socket and be connected with its second end at least indirectly to a battery of the motor vehicle; a storage compartment, in which the charging cable is received; a charging socket, which can be connected at least indirectly with the battery of the motor vehicle, and into which can be inserted a charging plug of a charging column; wherein the storage compartment includes the charging socket.