Abstract: Disclosed is a system including RF circuitry configured to generate an RF signal; a plurality of unit cells configured to receive the RF signal and to cause an RF energy signal having a center frequency to be present within the unit cells; and receiver circuitry configured to charge an electronic device in response to an antenna of the electronic device receiving the RF energy signal when the antenna is tuned to the center frequency and positioned in a near-field distance from one or more of the unit cells.

Abstract: A system includes charging segments positioned throughout a transportation network, the charging segments charging rechargeable electric vehicles. Each charging segment includes a primary coil to charge a selected rechargeable electric vehicle; a power inverter to convert alternating electrical current from a power grid to direct electrical current to pass through the primary coil; a switch to activate and deactivate the ability of the primary coil to charge the selected rechargeable electric vehicle; a transceiver to transmit signals to and receive signals from the selected rechargeable electric vehicle in spatial proximity to the charging segment; and a controller to control the switch in response to signals received from the transceiver.

Abstract: A battery charging apparatus includes a charging module and a control module. The control module obtains a DIR (dynamic internal resistance) of a battery cell group based on a voltage and a current of the battery cell group, and generates a control signal based on the voltage and the DIR of the battery cell group. The charging module alternates between outputting and not outputting a charge current/voltage to charge the battery cell group based on the control signal.

Abstract: An apparatus for preventing battery overcharge according to the present invention comprises: a voltage division unit having one end connected to a positive tap of a battery and the other end connected to a negative tap of the battery; and a switching unit having one end connected to the positive tap and the other end connected to the negative tap, the switching unit being shorted or opened according to a voltage divided from the voltage division unit. When a voltage between the positive tap and the negative tap is larger than or equal to a first voltage, the switching unit is shorted, the battery is shorted, an overcurrent is generated, the positive tap is destroyed, and the battery is electrically separated from a charging power source. The apparatus uses only passive devices, which makes it unnecessary to add a function for preventing an overcharge to a control unit, and has a simple construction enough to be added to a sensing circuit of a battery cell.

Abstract: A predictive electronic circuit design system, method, and apparatus provide the ability to design an electronic circuit. An electronic computer aided design (CAD) environment server computing device is connected to the Internet and includes a machine learning module program. The machine learning module program has a netlist analyzer program, a database, and a classifier and predictor program. The netlist analyzer program receives a circuit netlist for a designed circuit from a user, characterizes the circuit netlist, and sends characterization data to the database. Characterization data from multiple users for multiple designed circuits are stored in the database. The classifier and predictor program uses design goal data, the characterization data for multiple designed circuits, and simulation results, to calculate and produce predictions and proposals for the user to make design changes to the designed circuit in order to better meet or exceed design goals.

Abstract: A computer-implemented method obtains data describing a plurality of synthesis scenarios associated with a very-large-scale integration design (VLSI), wherein each synthesis scenario describes a different combination of tunable design parameters for a macro of the VLSI design, and wherein the VLSI design includes a plurality of macros being tuned. The plurality of macros is ranked based on the data. The ranking produces a macro waiting list that identifies those of the synthesis scenarios that are associated with each of the macros. A subset of the synthesis scenarios is pushed from the macro waiting list to a job submission queue that is separate from the macro waiting list. The job submission queue ranks the subset of synthesis scenarios in an order in which they are to be synthesized by a synthesis tuning system. At least one synthesis scenario is submitted to the synthesis tuning system according to the order.

Abstract: A computer-implemented method for optimizing microprocessor gates in a microprocessor includes receiving, via a processor, a dataset comprising a model of a plurality of gates of a microprocessor; determining, via the processor, whether a transmission line in the model, if implemented in a physical circuit, would result a signal transmission time less than a predetermined threshold time; applying to the model, via the processor, a proposed gate change to one or more of the plurality of gates; evaluating, via the processor and an area degradation based on the proposed gate change; determining, via the processor, a margin value based on the signal transmission time and an area degradation value; and making, via the processor, a gate change decision based on the margin value.

Abstract: Mechanisms for generating circuit paths are disclosed. A computing device obtains a nodal list that identifies a grid of nodes that is referenced to an area and that uniformly covers at least a portion of the area at a predetermined density. The computing device modifies the nodal list to identify a circuit path from a start node through a succession of neighbor nodes to an end node based on a waypoint list. For each of a plurality of iterations the computing device performs a bubble operation that includes identifying a first pair of nodes that are successive nodes in the circuit path and that are adjacent to a second pair of nodes out of the circuit path, and altering the circuit path to make the second pair of nodes part of the circuit path, such that the first pair of nodes are no longer successive nodes in the circuit path.

Abstract: An aspect of the present disclosure provides a hardware element in a Network on Chip (NoC), wherein the hardware element includes a clock gating circuit configures one or more neighboring hardware elements to activate before receiving new incoming data and to sleep after a defined number of cycles, wherein the defined number of cycles can be counted from a cycle having non-receipt of incoming data and/or having a clearance of all data within an input queue of a source hardware element.

Abstract: VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane.

Abstract: A high-voltage battery assembly includes a high-voltage battery electrically connected to a high-voltage bus including a positive rail and a negative rail, wherein the negative rail includes a controllable contactor switch. A boost charging module includes a DC-DC boost converter, a low-voltage power input line, a boost switch and a boost controller. The DC-DC boost converter is electrically connected to the low-voltage power input line via activation of the boost switch. The DC-DC boost converter connects to the positive rail. A low-voltage electrical connector is electrically connected to the low-voltage power input line of the DC-DC boost converter. The boost controller detects low-voltage power from the low-voltage electrical connector, detects that the controllable contactor switch, closes the boost switch, and controls the DC-DC boost converter to convert the low-voltage power on the low-voltage power input line to high-voltage power to charge the high-voltage battery.

Abstract: According to an aspect, a method includes accessing an initial layout of global wires and a congestion related metric for each net in a gate level design description of an integrated circuit. A second layout is accessed that specifies, for each net, detailed routing information that includes connections between specific wires in the regions of the integrated circuit. A list of nets with a same source region and target region in the initial layout as the failing net is generated. A net in the list of nets is selected and the failing net is rerouted over the selected net. The rerouting includes the global router updating the initial layout and the detailed router updating the second layout. The congestion related metric for each net is updated in response to the global router updating the initial layout.

Abstract: Electronic design automation systems, methods, and media are presented for hierarchical timing analysis with multi-instance blocks. Some embodiments involve generation of a combined timing context for all instances of a multi-instance block. Such embodiments may merge timing context information with multi-mode multi-context (MMMC) views for different instances of a multi-instance block. Other embodiments involve efficient merging of instance timing contexts during block level static timing analysis. Various different embodiments involve separate or hybrid merged timing analysis based on a user selection.

Abstract: Reducing the runtime overhead needed for testing of an integrated circuit design. A determination may be made of parameters that clock routing and data routing in an integrated circuit are dependent upon. A determination is made of whether the parameters are suitable for compaction, such as by determining whether the parameters are utilized in only one of clock routing or data routing. The parameters suitable for compaction are defined or redefined into at least one proxy compacted parameter. A timing analysis for the integrated circuit is performed using the proxy compacted parameter instead of performing the timing analysis using the parameters suitable for compaction.

Abstract: A system configured to receive and automatically analyze various types of information, including, without limitation, information from energy generators, information from non-generation resources, information on the facility status, information on user behavior, information on user's short-term energy needs (e.g. over-ride any algorithm due to immediate charging need), information on renewable generation, including, without limitation, solar, wind, biomass and/or hydro, and information on environmental conditions including, without limitation, barometric pressure, temperature, ambient light intensity, humidity, air speed, and air quality.

Abstract: Disclosed is a system including RF circuitry configured to generate an RF signal; a plurality of unit cells configured to receive the RF signal and to cause an RF energy signal having a center frequency to be present within the unit cells; and receiver circuitry configured to charge an electronic device in response to an antenna of the electronic device receiving the RF energy signal when the antenna is tuned to the center frequency and positioned in a near-field distance from one or more of the unit cells.

Abstract: A semiconductor device includes an edge active cell, an inner active cell and a middle active cell. The edge active cell is located near an edge of the semiconductor device. The edge active cell includes a plurality of fingers. The inner active cell is adjacent to the edge active cell toward a central portion of the semiconductor device. The inner active cell includes a plurality of fingers and at least one of the plurality of fingers of the edge active cell is electrically connected to at least one of the plurality of fingers of the inner active cell. The middle active cell is located near the central portion of the semiconductor device. The middle active cell includes a plurality of fingers and each of the fingers of the middle active cell is electrically connected to each other.

Abstract: This disclosure synthesizes an anodic composite material Li(LixNiyCozMnwO2+?) of Li2MnO3 series whose theoretical capacity is a level of about 460 mAh/g, and to produce an electrode of a high capacity using the synthesized anodic composite material. Also provided is a method for charging and discharging the electrode. Here, the method for producing an anodic composite material for a lithium secondary battery includes the steps of: mixing a nickel nitrate solution, a manganese nitrate solution, and a cobalt nitrate solution to produce a starting material solution; and mixing the starting material solution with a complexing agent so as to produce an anodic composite material Li(LixNiyCozMnwO2+?) of Li2MnO3 series by means of coprecipitation.

Abstract: The present invention provides a number of innovations in the area of computational process control (CPC). CPC offers unique diagnostic capability during chip manufacturing cycle by analyzing temporal drift of a lithography apparatus/ process, and provides a solution towards achieving performance stability of the lithography apparatus/process. Embodiments of the present invention enable optimized process windows and higher yields by keeping performance of a lithography apparatus and/or parameters of a lithography process substantially close to a pre-defined baseline condition. This is done by comparing the measured temporal drift to a baseline performance using a lithography process simulation model. Once in manufacturing, CPC optimizes a scanner for specific patterns or reticles by leveraging wafer metrology techniques and feedback loop, and monitors and controls, among other things, overlay and/or CD uniformity (CDU) performance over time to continuously maintain the system close to the baseline condition.

Abstract: Thermoelectric materials and thermoelectric cells and devices incorporating the thermoelectric materials are provided. Also provided are methods of using the cells and devices to generate electricity and to power external electronic devices. The thermoelectric materials comprise SnSe single crystals, including hole doped SnSe single crystals.