Abstract: Disclosed are methods and systems for characterizing and analyzing an electronic system design including a parallel interface. Some methods and systems identify an electronic design including a parallel interface, determine a single circuit representation including the parallel interface from the electronic design, and analyze the parallel interface to determine waveform responses of the parallel interface by using channel analysis techniques without performing circuit simulations.

Abstract: Disclosed is a communication terminal for constructing a daisy chain communication network without distinction between an input connector and an output connector.

Abstract: A wireless power transmitter that includes a power transmitting module, a communication module and a processing module is provided. The power transmitting module provides a wireless power to a wireless power receiver. The processing module receives a first request message from a remote mobile device through the communication module to request charging information of the wireless power receiver, determines whether the charging information is available, transmits available information to the remote mobile device under a condition that at least first part of the charging information is available, receives provided information from the wireless power receiver through the communication module under a condition that at least second part of the charging information is not available, and transmits the provided information through the communication module to the remote mobile device.

Abstract: A method for determining electrical parameter values of the transistors of an analog circuit of a system on chip includes breaking the circuit down into a set of blocks connected to one another; establishing the wiring diagram of said circuit; defining a set of electrical constraints that are specific to said circuit, blocks and transistors of each block; defining electrical parameters of the circuit, block and transistors; selecting for each transistor of the circuit an operator for calculating the electrical parameter values of said transistor; generating structured diagrams of each block of the circuit from the defined constraints and the chosen operators; assembling said structured diagrams of blocks into a general diagram of the circuit; identifying whether there is any conflict; and, if so, emitting an alarm signal.

Abstract: A power supply system effective to provide power to a plurality of different personal electronic devices includes a source of AC or DC power, a power converter effective to convert the AC or DC power to a useable voltage and amperage, a remote power outlet or a plurality of remote power outlets each configured to receive one or more connectors and a signal decoder. The signal decoder determines the requirements of a connected one of the personal entertainment devices and personal computing devices and apply the requirements to the power outlet for powering the device.

Abstract: Methods are disclosed to create efficient model-based Sub-Resolution Assist Features (MB-SRAF). An SRAF guidance map is created, where each design target edge location votes for a given field point on whether a single-pixel SRAF placed on this field point would improve or degrade the aerial image over the process window. In one embodiment, the SRAF guidance map is used to determine SRAF placement rules and/or to fine-tune already-placed SRAFs. The SRAF guidance map can be used directly to place SRAFs in a mask layout. Mask layout data including SRAFs may be generated, wherein the SRAFs are placed according to the SRAF guidance map. The SRAF guidance map can comprise an image in which each pixel value indicates whether the pixel would contribute positively to edge behavior of features in the mask layout if the pixel is included as part of a sub-resolution assist feature.

Abstract: A charging system for a multi-floor tower for the parking of electric vehicles includes a super capacitor, a charging port connecting with the electric vehicle, and a charging controller. The charging controller includes a diverter switch, a first current limited portion, a second current limited portion, and a charging control portion. The charging control portion is connected with the diverter switch, the super capacitor, and the charging port. The first current limited portion outputs a first stable current and is interconnected between the diverter switch and the charging port. The second current limited portion outputs a second stable current and is interconnected between the super capacitor and the charging port. The magnitude of the first stable current is larger than the magnitude of the second stable current.

Abstract: A circuit for protecting a battery for an electric vehicle includes a high voltage battery configured to output a DC voltage, an inverter configured to selectively receive the DC voltage from the high voltage battery and invert the DC voltage into an AC voltage when the inverter receives the DC voltage, a relay disposed between the high voltage battery and the inverter and configured to selectively block the DC voltage from the high voltage battery to the inverter, and a battery management system including a microchip configured to output a main relay control signal for controlling the relay. The battery management system is configured to receive the DC voltage from the high voltage battery, and output a voltage relay control signal controlling the relay separately from the control by the microchip.

Abstract: Systems and techniques for computing a timing effort metric are described. According to one definition, the computed timing effort metric indicates a level of difficulty of fixing a timing violation associated with a timing path between two circuit objects in a circuit design layout.

Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.

Abstract: Embodiments perform static timing analysis using a digital representation of a circuit. The digital representation of the circuit includes multiple instances of a cell in a hierarchical cell block circuit. Timing context information is determined for each instance of the cell included in the circuit. A merged timing context information is determined to bound and cover each of the plurality of instances of the cell. A slack estimate is determined for a pair of ports for each instance of the cell. The instance with the smallest slack estimate is identified. A slack estimate for a pair of ports of the cell is determined based on the merged timing information of the cell. A timing credit is determined for the pair of ports based on the slack of the instance with the smallest slack and the slack estimate from the bound information for the pair of ports.

Abstract: A method for designing a system on a target device utilizing programmable logic devices (PLDs) includes generating options for utilizing resources on the PLDs in response to user specified constraints. The options for utilizing the resources on the PLDs are refined independent of the user specified constraints.

Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.

Abstract: Disclosed herein is a reception device for wireless charging. The reception device for wireless charging may include a reception antenna configured to generate an electric current based on a change of magnetism and a charging circuit unit configured to convert the electric current generated by the reception antenna into direct current. The reception antenna and the charging circuit unit may be connected to a flexible board. Accordingly, the reception device can be attached to the casing of a smart terminal while minimizing a change in the thickness of the smart terminal. A task for connecting the antenna and charging circuit unit of the reception device can be eliminated. A wireless charging function can be assigned to a smart terminal by simply replacing the casing of the smart terminal not having the wireless charging function.

Abstract: Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information.

Abstract: An information processing apparatus includes a storage unit and a processor. The storage unit is configured to store therein plural pieces of shape data indicating shapes of a plurality of components. The plural pieces of shape data are associated with a first window for displaying unarranged components. The processor is configured to generate, using the plural pieces of shape data stored in the storage unit, display information for displaying a shape of a substrate on a screen and for displaying the first window including the shapes of the plurality of components on the displayed substrate. The processor is configured to output the display information.

Abstract: An integrated circuit includes a first circuit, a second circuit, and a bus that couples the circuits together. The first circuit is simulated on a first simulator at the same time that the second circuit is simulated on a second simulator. A simulator plug-in is incorporated into the simulation model of the first circuit. A simulator plug-in is incorporated into the simulation model of the second circuit. If valid data is to pass from the first to second circuit across the bus during simulation, then the plug-in of the first model causes a network stack to generate a packet. The packet carries the data. After communication to the second simulator, the data is recovered from the packet, and is injected by the plug-in of the second model into the simulation of the second circuit. By exchanging data back and forth this way, multiple circuits are simulated simultaneously on different simulators.

Abstract: Disclosed are techniques for enhancing timing analyses with reduced timing libraries for electronic designs. These techniques determine dominance relations for multiple timing models for timing analyses and generate a dominance adjacency data structure based at least in part upon the dominance relations. The dominance adjacency data structure may be stored at a first location of a non-transitory computer accessible storage medium. The plurality of timing models may be reduced into a reduced set of timing models at least by providing the dominance adjacency data structure as an input to a transformation and further by transforming the dominance adjacency data structure with the transformation into the reduced set of timing models that are used in timing analyses for an electronic design or a portion thereof.

Abstract: A method and system for management of electric charges of cells of an electricity storage battery, which are electrically connected in series and/or in parallel, the method including: balancing states of charge of the cells, performed only during a battery charging phase; and balancing quantities of charge contained in the cells, performed only during a battery discharging or rest phase.

Abstract: Systems and techniques are described for designing an integrated circuit (IC). Some embodiments identify and preserve slices by using new objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such slice objects. These new objects can enable rapid access and preservation of slices, thereby improving the runtime and/or quality of results (QoR) of an IC design system.