Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A method for selectively depositing a metallic film on a substrate comprising a first dielectric surface and a second metallic surface is disclosed. The method may include, exposing the substrate to a passivating agent, performing a surface treatment on the second metallic surface, and selectively depositing the metallic film on the first dielectric surface relative to the second metallic surface. Semiconductor device structures including a metallic film selectively deposited by the methods of the disclosure are also disclosed.

Abstract: A method for depositing silicon feedstock material may include introducing a first gas including silicon into a reactor chamber and introducing a second gas including at least one of gallium or indium into the reactor chamber and depositing silicon doped with at least one of gallium or indium onto a surface within the reactor chamber. Doped silicon feedstock material may be obtained by the method may be used for obtaining a silicon wafer, a solar cell, and/or a PV module.

Abstract: A method of manufacturing a semiconductor device is provided with: implanting charged particles including oxygen into a surface of a SiC wafer; and forming a Schottky electrode that makes Schottky contact with the SiC wafer on the surface after the implantation of the charged particles.

Abstract: A semiconductor chip (100) is provided, having a first semiconductor layer (1), which has a lateral variation of a material composition along at least one direction of extent. Additionally provided is a method for producing a semiconductor chip (100).

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices. In particular, the present disclosure relates to shielding regions for use in combination with an optimization layer. The disclosed shielding regions reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed shielding regions occupy a portion of the JFET region between adjacent device cells and interrupt the continuity of the optimization layer in a widest portion of the JFET region, where the corners of neighboring device cells meet. The disclosed shielding regions and device layouts enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

Abstract: A device includes a first light-emitting device and a second light-emitting device, each including an anode, a cathode, charge transport layers disposed between the anode and the cathode, and an emissive layer disposed between the charge transport layers. For the first light-emitting device, the emissive layer includes first quantum dots, the emissive layer configured to emit light at a first wavelength. For the second light-emitting device, the emissive layer includes emissive sub-layers provided in a stacked arrangement in a thickness direction. A first one of the emissive sub-layers includes the first quantum dots and is configured to emit light at the first wavelength, and a second one of the emissive sub-layers includes second quantum dots and is configured to emit light at a second wavelength different than the first wavelength.

Abstract: A method of making nanoscale devices, the method including: depositing a metal film on a surface of a first substrate; annealing the metal film to form a plurality of metal island structures on the surface of the first substrate; laying metal nanospheres on the surface of the first substrate; baking the first composite structure to make the metal nanospheres become a plurality of metal crystalline balls; forming a photoresist layer on the first surface of the second composite structure; placing a release agent layer on a second substrate, applying an external force to press the photoresist layer on the release agent layer under an inert atmosphere; heating the second composite structure, the photoresist layer, the release agent layer, and the second substrate are and applying voltages in three stages.

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Abstract: A light-emitting element disclosed according to an embodiment may comprise: a substrate comprising a body, a plurality of lead electrodes arranged over the body in a first axial direction, and a heat-radiating frame and a plurality of lead frames arranged below the body in a second axial direction; and a light-emitting chip arranged on a first lead electrode, which is arranged in the central area of the body among the plurality of lead electrodes, and electrically connected with the plurality of lead electrodes. The plurality of lead electrodes have a large length in the second axial direction, the heat-radiating frame is arranged in the central area below the body, and the heat-radiating frame and the plurality of lead frames have a large length in the first axial direction and may vertically overlap with the plurality of lead electrodes.

Abstract: A structure with an interconnection layer for redistribution of electrical connections includes a plurality of first electrical connections disposed on a substrate in a first arrangement. An insulating layer is disposed on the substrate over the first electrical connections. A plurality of second electrical connections is disposed on the insulating layer on a side of the insulating layer opposite the plurality of first electrical connections in a second arrangement. Each second electrical connection is electrically connected to a respective first electrical connection. An integrated circuit is disposed on the substrate and is electrically connected to the first electrical connections. The first electrical connections in the first arrangement have a greater spatial density than the second electrical connections in the second arrangement.

Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a semiconductor-on-insulator device is provided. The single crystal semiconductor handle wafer is prepared to comprise a charge trapping layer, which is oxidized. The buried oxide layer in the resulting semiconductor-on-insulator device comprises an oxidized portion of the charge trapping layer and an oxidized portion of the single crystal semiconductor device layer.

Abstract: Embodiments of the invention include conductive vias and methods for forming the conductive vias. In one embodiment, a via pad is formed over a first dielectric layer and a photoresist layer is formed over the first dielectric layer and the via pad. Embodiments may then include patterning the photoresist layer to form a via opening over the via pad and depositing a conductive material into the via opening to form a via over the via pad. Embodiments may then includeremoving the photoresist layer and forming a second dielectric layer over the first dielectric layer, the via pad, and the via. For example a top surface of the second dielectric layer is formed above a top surface of the via in some embodiments. Embodiments may then include recessing the second dielectric layer to expose a top portion of the via.

Abstract: A method of pattern transfer is provided, comprising: providing a target layer; forming a first pattern above the target layer; forming a second pattern (such as spacer loops) above the target layer and above the first pattern, wherein one closed end of the second pattern partially overlaps with the first pattern; and transferring the second pattern to the target layer, wherein the first pattern stops transferring pattern of the closed end of the second pattern to the target layer.

Abstract: A method of forming a semiconductor device includes forming a first dummy gate structure over a substrate, forming gate spacers over the substrate, cutting the first dummy gate structure to form separated dummy gate portions, forming a dielectric feature between the dummy gate portions, and performing a thermal process to the dielectric feature to contract the dielectric feature, wherein the contraction of the dielectric feature deforms at least one of the gate spacers such that a distance between the gate spacers is increased.

Abstract: A semiconductor device includes an integrated circuit, at least one outer seal ring, and at least one inner seal ring. The outer seal ring surrounds the integrated circuit. The outer seal ring includes a plurality of metal layers in a stacked configuration, and the metal layers are closed loops. The inner seal ring is disposed between the outer seal ring and the integrated circuit and separated from the outer seal ring. The inner seal ring has at least one gap extending from a region encircled by the inner seal ring to a region outside the inner seal ring.

Abstract: A compound or a resin represented by the following formula (1).

Abstract: A material for forming an underlayer film for lithography, in which a compound represented by the following formula (0) is used.

Abstract: A method for manufacturing a semiconductor device includes forming a first mask layer having a first opening on an underlying layer; forming a first layer in a space where the underlying layer is selectively removed via the first opening; forming a second mask layer on the first mask layer and the first layer, the second mask layer having a second opening crossing the first opening; and selectively removing the first layer at a portion where the first opening and the second opening cross. At least one of the first and second mask layers having openings including the first or second opening, the openings being arranged in the first mask layer along a first direction, and/or being arranged in the second mask layer along a second direction, the first opening crossing the second opening in the first direction, and the second opening crossing the first opening in the second direction.

Abstract: Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.