Abstract: A radiation detector comprises an antenna structure; and a field effect transistor structure having a source region, a gate region, and a drain region, arranged on a substrate and forming mutually independent electrically conductive electrode structures through metallization, wherein the gate electrode structure completely encloses the source electrode structure or the drain electrode structure in a first plane; the enclosed electrode structure extends up to above the gate electrode structure and there overlaps the enclosure in a second plane above the first plane at least in sections in a planar manner; wherein an electrically insulating region for forming a capacitor with a metal-insulator-metal structure is arranged between the regions of the gate electrode structure overlapped by the enclosed electrode structure.

Abstract: A light emitting diode package includes an upper housing and a lower housing. The upper housing includes a first light emitting diode (LED) chip arranged therein, a second LED chip arranged to be spaced apart from the first LED chip in a first direction, two light discharge structures, first electrodes formed on a lower surface of the first LED chip, and second electrodes formed on a lower surface of the second LED chip. The lower housing includes at least three grooves at a lower surface thereof. The lower housing further includes three or more pads. The first pair of via-holes are arranged to connect the first electrodes to one or more of the pads in a second direction perpendicular to the first direction. The second pair of via-holes are arranged to connect the second electrodes to one or more of the pads in the second direction.

Abstract: The invention aims for a wafer edge trimming method 1 adhered on a support wafer 2 by way of an interface layer 3. A zone at the perimeter 12 of the wafer 1 is trimmed by grinding. The stopping of the grinding is advantageously done at the level of the interface layer 3. To do this, an interface layer 3 comprising a transition layer 4 having a resistance to grinding greater than that of the wafer 1 is used. According to a possibility, detecting an increase of the resistance to grinding during the grinding is done, so as to stop the grinding.

Abstract: A semiconductor device includes a substrate having a semiconductor fin, an isolation feature over the substrate and not overlapping the semiconductor fin, a first gate structure over the substrate, and a second gate structure over the substrate. The isolation feature is closer to the first gate structure than the second gate structure. The first gate structure has a maximum width greater than a maximum width of the second gate structure.

Abstract: A packaged electronic circuit includes a substrate having an upper surface, a first metal layer on the upper surface of the substrate, a first polymer layer on the first metal layer opposite the substrate, a second metal layer on the first polymer layer opposite the first metal layer, a dielectric layer on the first polymer layer and at least a portion of the second metal layer and a second polymer layer on the dielectric layer.

Abstract: In an embodiment, a method includes: performing a self-limiting process to modify a top surface of a wafer; after the self-limiting process completes, removing the modified top surface from the wafer; and repeating the performing the self-limiting process and the removing the modified top surface from the wafer until a thickness of the wafer is decreased to a predetermined thickness.

Abstract: In various embodiments, disclosed herein are systems and methods directed to the fabrication of a coreless semiconductor package (e.g., a millimeter (mm)-wave antenna package) having an asymmetric build-up layer count that can be fabricated on both sides of a temporary substrate (e.g., a core). The asymmetric build-up layer count can reduce the overall layer count in the fabrication of the semiconductor package and can therefore contribute to fabrication cost reduction. In further embodiments, the semiconductor package (e.g., a millimeter (mm)-wave antenna packages) can further comprise dummification elements disposed near one or more antenna layers. Further, the dummification elements disposed near one or more antenna layers can reduce image current and thereby increasing the antenna gain and efficiency.

Abstract: Disclosed in the present invention are a sensor packaging structure and a manufacturing method thereof. The sensor packaging structure includes a protection board, a circuit structure and a filling structure. A front surface of the circuit structure is connected to a first surface of the protection board. A second surface of the protection board is used as a sensing function surface. The filling structure is located on the outer periphery of the circuit structure and connected to the first surface of the protection board. The sensor packaging structure of the present invention uses the protection board as a protection layer of the functional circuit, which can effectively protect the functional circuit of the sensor. Meanwhile, the protection board is first connected to the circuit structure in the manufacturing method to avoid tolerance accumulation, increasing the manufacturing accuracy of the protection layer.

Abstract: A method of manufacturing a semiconductor device includes forming an etch target layer on a substrate; forming an amorphous metal layer on the etch target layer, the amorphous metal layer comprising nitrogen between 15 atomic percentage (at %) and 25 at %; forming an amorphous metal hardmask by patterning the amorphous metal layer; and etching the etch target layer by using the amorphous metal hardmask as an etching mask.

Abstract: A memory device includes a first state transistor and a second state transistor having a common control gate. A first selection transistor is buried in the semiconductor body and coupled to the first state transistor so that current paths of the first selection transistor and first state transistor are coupled in series. A second selection transistor is buried in the semiconductor body and coupled to the second state transistor so that current paths of the second selection transistor and second state transistor are coupled in series. The first and second selection transistors have a common buried selection gate. A dielectric region is located between the common control gate and the semiconductor body. A first bit line is coupled to the first state transistor and a second bit line is coupled to the second state transistor.

Abstract: The present disclosure relates to an air-cavity module having a thinned semiconductor die and a mold compound. The thinned semiconductor die includes a back-end-of-line (BEOL) layer, an epitaxial layer over the BEOL layer, and a buried oxide (BOX) layer with discrete holes over the epitaxial layer. The epitaxial layer includes an air-cavity, a first device section, and a second device section. Herein, the air-cavity is in between the first device section and the second device section and directly in connection with each discrete hole in the BOX layer. The mold compound resides directly over at least a portion of the BOX layer, within which the discrete holes are located. The mold compound does not enter into the air-cavity through the discrete holes.

Abstract: An integrated circuit includes transistor devices, each having a back gate. A controller is connected to the back gate to apply voltages to the back gate, wherein a first mode includes a first voltage for operational threshold voltages for the transistor devices, and a second mode includes a second voltage that enhances threshold voltage variability of the plurality of transistor devices to provide a physically unclonable function (PUF) for chip identification.

Abstract: The present disclosure relates to a wafer-level package that includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes redistribution interconnects that connect the first device layer to package contacts on a bottom surface of the multilayer redistribution structure. Herein, the connections between the redistribution interconnects and the first device layer are solder-free. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define an opening within the first mold compound and over the first thinned die. The second mold compound fills the opening and is in contact with the top surface of the first thinned die.

Abstract: A method for producing an organic EL device having an anode, a cathode, at least one organic functional layer disposed between the anode and the cathode, and a sealing layer, comprising a step of forming the anode, a step of forming the cathode, a step of forming the at least one organic functional layer and a step of forming the sealing layer, wherein the average concentration: A (ppm) of ammonia to which the organic EL device during production is exposed from initiation time of the step of forming the at least one organic functional layer until termination time of the step of forming the sealing layer and the exposure time thereof: B (sec) satisfy the formula (1-1): 0?A×B?105??(1-1).

Abstract: Examples include a method for forming an intermediate in the fabrication of a field-effect transistor sensor, the method comprising: providing a substrate having a substrate region comprising a gate dielectric thereon and optionally a nanocavity therein, providing a sacrificial element over the substrate region, providing one or more layers having a combined thickness of at least 100 nm over the sacrificial element, opening an access to the sacrificial element through the one or more layers, and optionally selectively removing the sacrificial element, thereby opening a sensor cavity over the substrate region; wherein the sacrificial element is removable by oxidation and wherein selectively removing the sacrificial element comprises an oxidative removal.

Abstract: Methods and systems for determining band structure characteristics of high-k dielectric films deposited over a substrate based on spectral response data are presented. High throughput spectrometers are utilized to quickly measure semiconductor wafers early in the manufacturing process. Optical models of semiconductor structures capable of accurate characterization of defects in high-K dielectric layers and embedded nanostructures are presented. In one example, the optical dispersion model includes a continuous Cody-Lorentz model having continuous first derivatives that is sensitive to a band gap of a layer of the unfinished, multi-layer semiconductor wafer. These models quickly and accurately represent experimental results in a physically meaningful manner. The model parameter values can be subsequently used to gain insight and control over a manufacturing process.

Abstract: Systems and methods are provided for producing an integrated circuit package, e.g., an SOIC package, having reduced or eliminated lead delamination caused by epoxy outgassing resulting from the die attach process in which an integrated circuit die is attached to a lead frame by an epoxy. The epoxy outgassing may be reduced by heating the epoxy during or otherwise in association with the die attach process, e.g. using a heating device provided at the die attach unit. Heating the epoxy may achieve additional cross-linking in the epoxy reaction, which may thereby reduce outgassing from the epoxy, which may in turn reduce or eliminate subsequent lead delamination. A heating device located at or near the die attach site may be used to heat the epoxy to a temperature of 55° C.±5° C. during or otherwise in association with the die attach process.

Abstract: A semiconductor package includes a first layer of one or more first semiconductor chips each having a first surface at which one or more first pads are exposed, a second layer of one or more second semiconductor chips disposed over the first layer and each having a second surface at which one or more second pads are exposed, and a first redistribution layer between the first layer and the second layer and electrically connected to the one or more first pads. The first layer may include one or more first TPVs extending through a substrate (panel) of the first layer and electrically connected to the first redistribution layer.

Abstract: A group III nitride laminate having monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and an electrode is provided. The group III nitride laminate is characterized in that an n-type contact layer made of (AlYGa1-Y)2O3 (0.0?Y<0.3) is provided between the monocrystalline n-type AlxGa1-xN (0.7?X?1.0) and the electrode. Furthermore, a vertical semiconductor device including the above-described group III nitride laminate is provided.

Abstract: An embodiment relates to a semiconductor device, a semiconductor device package, and a method for producing a semiconductor device, the semiconductor device comprising a light emitting structure including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, and an intermediate layer disposed between the first conductivity type semiconductor layer and the active layer, or disposed inside the first conductivity type semiconductor layer, wherein the first conductivity type semiconductor layer, the intermediate layer, the active layer, and the second conductivity type semiconductor layer include aluminum, and the intermediate layer includes a first intermediate layer having a lower aluminum composition than that of the first conductivity type semiconductor layer.