Patents Examined by Bob M Kunemund
  • Patent number: 9109301
    Abstract: In a crystalline silicon formation apparatus, a quick cooling method is applied to the bottom of a crucible to control a growth orientation of a polycrystalline silicon grain, such that the crystal grain forms twin boundary, and the twin boundary is a symmetric grain boundary, and the crystal grain is solidified and grown upward in unidirection to form a complete polycrystalline silicon, such that defects or impurities will not form in the polycrystalline silicon easily.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: August 18, 2015
    Assignee: Sino-American Silicon Products, Inc.
    Inventors: Chung-Wen Lan, Kimsam Hsieh, Wen-Huai Yu, Bruce Hsu, Ya-Lu Tsai, Wen-Ching Hsu, Suz-Hua Ho
  • Patent number: 9080254
    Abstract: In a method of producing a SiC single crystal, the SiC single crystal is grown on a SiC seed crystal by bringing the SiC seed crystal, which is fixed at a rotatable seed crystal fixing shaft, into contact with a solution produced by dissolving carbon in melt containing silicon in a rotatable crucible. The method includes starting rotation of the seed crystal fixing shaft, and starting rotation of the crucible after a predetermined delay time (Td); then stopping the rotation of the seed crystal fixing shaft and the rotation of the crucible simultaneously; then stopping the seed crystal fixing shaft and the crucible for a predetermined stop time (Ts); and repeating a rotation/stop cycle.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: July 14, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidemitsu Sakamoto, Hironori Daikoku, Yasuyuki Fujiwara
  • Patent number: 9068278
    Abstract: Embodiments of the invention are provided for a thin film stack containing a plurality of epitaxial stacks disposed on a substrate and a method for forming such a thin film stack. In one embodiment, the epitaxial stack contains a first sacrificial layer disposed over the substrate, a first epitaxial film disposed over the first sacrificial layer, a second sacrificial layer disposed over the first epitaxial film, and a second epitaxial film disposed over the second sacrificial layer. The thin film stack may further contain additional epitaxial films disposed over sacrificial layers. Generally, the epitaxial films contain gallium arsenide alloys and the sacrificial layers contain aluminum arsenide alloys. Methods provide the removal of the epitaxial films from the substrate by etching away the sacrificial layers during an epitaxial lift off (ELO) process. The epitaxial films are useful as photovoltaic cells, laser diodes, or other devices or materials.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: June 30, 2015
    Assignee: Alta Devices, Inc.
    Inventors: Gang He, Andreas Hegedus
  • Patent number: 9062390
    Abstract: Methods of forming a crystalline strontium titanate layer may include providing a substrate with a crystal enhancement surface (e.g., Pt), depositing strontium titanate by atomic layer deposition, and conducting a post-deposition anneal to crystallize the strontium titanate. Large single crystal domains may be formed, laterally extending greater distances than the thickness of the strontium titanate and demonstrating greater ordering than the underlying crystal enhancement surface provided to initiate ALD. Functional oxides, particularly perovskite complex oxides, can be heteroepitaxially deposited over the crystallized STO.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: June 23, 2015
    Assignee: ASM International N.V.
    Inventor: Tom E. Blomberg
  • Patent number: 9051661
    Abstract: Silicon single crystals having suppressed deformation and dislocations and the successful omission of the tail section are produced by growing the straight-body section of the silicon single crystal under the influence of a horizontal magnetic field with a magnetic flux density at its magnetic center being ?1000 Gauss, and ?2000 Gauss, reducing the lifting speed of the silicon single crystal relative to the surface of the melt to 0 mm/minute, maintaining a static state until there is a decrease in the apparent weight of the silicon single crystal, then further maintaining the static state so that the entire growth front of the silicon single crystal forms a convex shape protruding in a direction opposite to the lifting direction of the silicon single crystal, and separating the silicon single crystal from the melt.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: June 9, 2015
    Assignee: Siltronic AG
    Inventor: Shinichi Kyufu
  • Patent number: 9028611
    Abstract: A method for producing a Group III nitride semiconductor includes reacting a molten mixture containing at least a Group III element and an alkali metal with a gas containing at least nitrogen, to thereby grow a Group III nitride semiconductor crystal on the seed crystal. The method includes forming a template substrate including a sapphire substrate and a first Group III nitride semiconductor layer as the seed crystal which is formed by vapor phase growth and which includes a c-plane as a main plane is employed, and the template substrate is placed and maintained in the molten mixture under conditions where crystal growth of the Group III nitride semiconductor is inhibited, to thereby partially melt back a plurality of separated parts of the first Group III nitride semiconductor layer to such a depth that the sapphire substrate is partially exposed.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: May 12, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Shiro Yamazaki
  • Patent number: 9023152
    Abstract: A solution-stirring top-seeded solution-growth method for forming CLBO of the type where water is added to a precursor mixture, where heavy water is substituted for the water.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: May 5, 2015
    Assignee: KLA-Tencor Corporation
    Inventor: Vladimir L. Dribinski
  • Patent number: 9017477
    Abstract: Provided is a process for producing colloidal crystals from which a large single crystal reduced in lattice defects and unevenness can be easily produced at low cost without fail. The process for colloidal crystal production comprises: preparing a colloidal polycrystal dispersion in which colloidal crystals precipitate at a given temperature (preparation step); introducing into a vessel The colloidal polycrystal dispersion in the state of containing fine colloidal polycrystals precipitated (introduction step); and melting the colloidal polycrystals and then recrystallizing the molten polycrystals (recrystallization step). The crystals thus obtained have fewer lattice defects and less unevenness than the original polycrystals.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: April 28, 2015
    Assignees: Nagoya City University, Fuji Chemical Co., Ltd.
    Inventors: Junpei Yamanaka, Mariko Shinohara, Akiko Toyotama, Koki Yoshizawa, Sachiko Onda, Masakatsu Yonese, Fumio Uchida
  • Patent number: 9011599
    Abstract: A method of determining a temperature in a deposition reactor includes the steps of depositing a first epitaxial layer of silicon germanium on a substrate, depositing a second epitaxial layer of silicon above the first epitaxial layer, measuring the thickness of the second epitaxial layer and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer. The method may also include heating the deposition reactor to approximately a predetermined temperature using a heating device and a temperature measuring device and generating a signal indicative of a temperature within the deposition reactor. The method may also contain the steps of comparing the measured thickness with a predetermined thickness of the second epitaxial layer corresponding to the predetermined temperature and determining the temperature in the deposition reactor using the measured thickness of the second epitaxial layer and the predetermined thickness of the second epitaxial layer.
    Type: Grant
    Filed: July 14, 2010
    Date of Patent: April 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhi-Cherng Lu, Jr-Hung Li, Chii-Horng Li, Pang-Yen Tsai, Bing-Hung Chen, Tze-Liang Lee
  • Patent number: 9005362
    Abstract: The present invention is to provide a method for growing a group III nitride crystal that has a large size and has a small number of pits formed in the main surface of the crystal by using a plurality of tile substrates. A method for growing a group III nitride crystal includes a step of preparing a plurality of tile substrates 10 including main surfaces 10m having a shape of a triangle or a convex quadrangle that allows two-dimensional close packing of the plurality of tile substrates; a step of arranging the plurality of tile substrates 10 so as to be two-dimensionally closely packed such that, at any point across which vertexes of the plurality of tile substrates 10 oppose one another, 3 or less of the vertexes oppose one another; and a step of growing a group III nitride crystal 20 on the main surfaces 10m of the plurality of tile substrates arranged.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: April 14, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yuki Hiromura, Koji Uematsu, Hiroaki Yoshida, Shinsuke Fujiwara
  • Patent number: 8999058
    Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: April 7, 2015
    Assignee: Solexel, Inc.
    Inventors: George D. Kamian, Somnath Nag, Subbu Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
  • Patent number: 8986446
    Abstract: This invention provides an Si doped GaAs single crystal ingot, which has a low crystallinity value as measured in terms of etch pit density (EPD) per unit area and has good crystallinity, and a process for producing the same. An Si-doped GaAs single crystal wafer produced in a latter half part in the growth of the Si doped GaAs single crystal ingot is also provided. A GaAs compound material is synthesized in a separate synthesizing oven (a crucible). An Si dopant is inserted into the compound material to prepare a GaAs compound material with the Si dopant included therein. The position of insertion of the Si dopant is one where, when the GaAs compound material is melted, the temperature is below the average temperature. After a seed crystal is inserted into a crucible for an apparatus for single crystal growth, the GaAs compound material with the Si dopant included therein and a liquid sealing compound are introduced into the crucible.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: March 24, 2015
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventor: Yoshikazu Oshika
  • Patent number: 8986447
    Abstract: A high pressure apparatus and related methods for processing supercritical fluids. In a specific embodiment, the present apparatus includes a capsule, a heater, at least one ceramic ring but can be multiple rings, optionally, with one or more scribe marks and/or cracks present. In a specific embodiment, the apparatus optionally has a metal sleeve containing each ceramic ring. The apparatus also has a high-strength enclosure, end flanges with associated insulation, and a power control system. In a specific embodiment, the apparatus is capable of accessing pressures and temperatures of 0.2-2 GPa and 400-1200° C., respectively.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: March 24, 2015
    Assignee: Soraa, Inc.
    Inventor: Mark P. D'Evelyn
  • Patent number: 8986448
    Abstract: To provide a method of manufacturing a single crystal 3C-SiC substrate that can dramatically reduce surface defects generated in a processing of epitaxial growth and can secure a quality as a semiconductor device while simplifying a post process. The method of manufacturing a single crystal 3C-SiC substrate where a single crystal 3C-SiC layer is formed on a base substrate by epitaxial growth is provided. A first growing stage of forming the single crystal 3C-SiC layer to have a surface state configured with a surface with high flatness and surface pits scattering in the surface is performed. A second growing stage of further epitaxially growing the single crystal 3C-SiC layer obtained in the first growing stage so as to fill the surface pits is performed.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: March 24, 2015
    Assignee: Air Water Inc.
    Inventors: Hidetoshi Asamura, Keisuke Kawamura, Satoshi Obara
  • Patent number: 8979999
    Abstract: A method for large-scale manufacturing of gallium nitride boules. Large-area single crystal seed plates are suspended in a rack, placed in a large diameter autoclave or internally-heated high pressure apparatus along with ammonia and a mineralizer, and grown ammonothermally. The seed orientation and mounting geometry are chosen to provide efficient utilization of the seed plates and of the volume inside the autoclave or high pressure apparatus. The method is scalable up to very large volumes and is cost effective.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: March 17, 2015
    Assignee: Soraa, Inc.
    Inventor: Mark P. D'Evelyn
  • Patent number: 8974599
    Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described., as well as a system for use in performing such a method, and articles incorporating such a composition.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: March 10, 2015
    Assignee: SCIO Diamond Technology Corporation
    Inventors: Robert C. Linares, Patrick J. Doering
  • Patent number: 8968469
    Abstract: A structure including a substrate, an intermediate layer provided and formed directly onto the substrate, a transition region, and a group II-VI bulk crystal material provided and formed as an extension of the transition region. The transition region acts to change the structure from the underlying substrate to that of the bulk crystal. In a method of manufacture, a similar technique can be used for growing the transition region and the bulk crystal layer.
    Type: Grant
    Filed: October 11, 2010
    Date of Patent: March 3, 2015
    Assignee: Kromek Limited
    Inventors: Arnab Basu, Max Robinson, Ben Cantwell, Andy Brinkman
  • Patent number: 8961686
    Abstract: For manufacturing a monocrystal, a monocrystal pulling-up device controls pressure within a flow straightening cylinder to be from 33331 Pa to 79993 Pa and a flow velocity of inert gas in the cylinder to be from 0.06 m/sec to 0.31 m/sec (0.005 to 0.056 SL/min·cm2) during a post-addition-pre-growth period. By controlling the flow velocity of the inert gas to be in the above-described range during the post-addition-pre-growth period, the inert gas flows smoothly even when the pressure within the cylinder is relatively high. Evaporation of a volatile dopant because of a reverse flow of the inert gas can be restrained. The volatile dopant can be prevented from adhering to the flow straightening cylinder in an amorphous state, and the volatile dopant can be prevented from dropping into a melt or sticking on the melt while growing a crystal. Foulings can be easily removed.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: February 24, 2015
    Assignee: Sumco Techxiv Corporation
    Inventors: Shinichi Kawazoe, Fukuo Ogawa, Yasuhito Narushima, Toshimichi Kubota
  • Patent number: 8961687
    Abstract: Disclosed embodiments include methods of fabricating a semiconductor layer or device and devices fabricated thereby. The methods include, but are not limited to, providing a substrate having a cubic crystalline surface with a known lattice parameter and growing a cubic crystalline group III-nitride alloy layer on the cubic crystalline substrate by coincident site lattice matched epitaxy. The cubic crystalline group III-nitride alloy may be prepared to have a lattice parameter (a?) that is related to the lattice parameter of the substrate (a). The group III-nitride alloy may be a cubic crystalline InxGayAl1-x-yN alloy. The lattice parameter of the InxGayAl1-x-yN or other group III-nitride alloy may be related to the substrate lattice parameter by (a?)=?2(a) or (a?)=(a)/?2. The semiconductor alloy may be prepared to have a selected band gap.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: February 24, 2015
    Assignee: Alliance for Sustainable Energy, LLC
    Inventors: Andrew G. Norman, Aaron J. Ptak, William E. McMahon
  • Patent number: 8956453
    Abstract: The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H2 flux or hydrogen originating from dissociation of GeH4 and/or to a non-reactive gas source such as N2, He, Ne, Ar, Kr, Xe, Rn or mixtures thereof, and crystallizing the amorphous germanium layer by annealing the base substrate so as to provide a crystalline germanium layer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 17, 2015
    Assignees: IMEC, Vrije Universiteit Brussel
    Inventors: Ruben Lieten, Stefan Degroote