Patents Examined by Bradley K Smith
  • Patent number: 10297451
    Abstract: A method of manufacturing a memory device includes: providing a substrate; forming in a cell region a channel extending in a direction perpendicular to an upper surface of the substrate and a plurality of gate electrode layers and a plurality of insulating layers stacked alternatingly on the substrate to be adjacent to the channel; forming a plurality of circuit elements on the substrate at a peripheral circuit region disposed at a periphery of the cell region; and forming an interlayer insulating layer on the substrate in the cell region and the peripheral circuit region, the interlayer insulating layer including a first, bottom interlayer insulating layer covering the plurality of circuit elements and at least a portion of the plurality of gate electrode layers, and a second, top interlayer insulating layer disposed on the first interlayer insulating layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: May 21, 2019
    Inventors: Won Seok Jung, Joon Hee Lee, Keon Soo Kim, Sun Yeong Lee
  • Patent number: 10217837
    Abstract: A semiconductor device includes a semiconductor mesa having source zones and at least one body zone forming first pn junctions with the source zones and a second pn junction with a drift zone. Electrode structures are provided on opposite sides of the semiconductor mesa, at least one of the electrode structures having a gate electrode configured to control a charge carrier flow through the at least one body zone. A separation region is arranged along an extension direction of the semiconductor mesa. In the separation region, the semiconductor mesa has a constricted portion that is partially or completely oxidized. Additional semiconductor device embodiments are described.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 26, 2019
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Matteo Dainese, Peter Lechner, Hans-Joachim Schulze, Johannes Georg Laven
  • Patent number: 10211164
    Abstract: A plurality of semiconductor packages are manufactured by a method that includes the steps of bonding a plurality of semiconductor chips on the front side of a wiring substrate, next supplying a sealing compound to the front side of the wiring substrate to form a resin layer from the sealing component on the front side of the wiring substrate, thereby forming a sealed substrate including the wiring substrate and the resin layer covering the semiconductor chips, next cutting the sealed substrate from the resin layer side by using a V blade to thereby form a V groove along each division line, next dividing the wiring substrate along each V groove to obtain a plurality of individual bare packages, and finally forming an electromagnetic shield layer on the upper surface and an inclined side surface of each bare package, thereby obtaining the plural semiconductor packages.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: February 19, 2019
    Inventors: Youngsuk Kim, Byeongdeck Jang, Fumio Uchida
  • Patent number: 10204977
    Abstract: Each of a first and a second integrated circuit structures has hole(s) in the top surface, and capacitors at least partially located in the holes. A semiconductor die is attached to the top surface of the second structure. Then the first and second structures are bonded together so that the die becomes disposed in the first structure's cavity, and the holes of the two structures are aligned to electrically connect the respective capacitors to each other. A filler is injected into the cavity through one or more channels in the substrate of the first structure. Other embodiments are also provided.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 12, 2019
    Inventors: Liang Wang, Hong Shen, Rajesh Katkar
  • Patent number: 10205048
    Abstract: A method for manufacturing a light emitting diode (LED) chip comprises steps of stacking together a first substrate, a buffer layer, an ultraviolet light (UV) shielding layer, and at least one LED chip in that sequence. An orthogonal projection of each LED chip on the UV shielding layer is located in the scope of the UV shielding layer, and a periphery of the UV shielding layer protrudes from a periphery of the orthogonal projection; mounting a side of each LED chip facing away from the first substrate on the second substrate with an adhesive layer; irradiating UV light from a side of the first substrate facing away from the LED chip, to separate the first substrate from the UV shielding layer; removing the UV light shielding layer, the second substrate, and the adhesive layer from each LED chip.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: February 12, 2019
    Inventors: Po-Min Tu, Tzu-Chien Hung, Chia-Hui Shen, Chien-Shiang Huang, Chien-Chung Peng
  • Patent number: 10181586
    Abstract: The invention relates to an organic light-emitting component which has an organic functional layer stack (3) having at least one light-emitting layer, which is designed to generate light during operation of the component, a transparent first electrode (2) and a transparent second electrode (4), which are designed to inject charge carriers into the organic functional layer stack (3) during operation, and a heat distribution layer (9), which is applied over the electrodes (2, 4) and the organic functional layer stack (3) and which has at least one plastic layer (10) and a highly heat conductive layer (11), wherein the heat distribution layer (9) has at least one transparent sub-region (91) and at least one non-transparent sub-region (92).
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: January 15, 2019
    Assignee: OSRAM OLED GMBH
    Inventors: Simon Schicktanz, Philipp Schwamb
  • Patent number: 10177242
    Abstract: A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 8, 2019
    Inventors: Tai-I Yang, Tien-Lu Lin, Wai-Yi Lien, Chih-Hao Wang, Jiun-Peng Wu
  • Patent number: 10173338
    Abstract: Method (500) and calculating unit (620) for curve sawing of a block (100) in a cutting direction (S) with at least a first circular saw blade (110). The method (500) comprises determining (501) a radius (R) of the curve sawing, by measuring the curvature of the block (100) in the direction of cutting (S); calculating (502) a vertical inclination angle (?) of the first circular saw blade (110) in a vertical plane (V) relative to the cutting direction (S) in the block (100), based on the determined radius (R) of the curve sawing; inclining (503) the first circular saw blade (110) with the calculated (502) vertical inclination angle (?); and sawing (508) the block (100) in the cutting direction (S) with the inclined (503) first circular saw blade (110) along the determined (501) radius (R) of the curve sawing.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: January 8, 2019
    Assignee: Soderhamm Eriksson AB
    Inventor: Mats Ekevad
  • Patent number: 10157857
    Abstract: The present disclosure is drawn to, among other things, a method of forming a semiconductor shield from a stock material having a thickness. In some aspects the methods includes providing a first layer of material on a first surface of the stock material, wherein at least a portion of the first layer of material includes a first window that exposes a portion of the first surface; providing a second layer of material on a second surface of the stock material, wherein the second surface of the stock material is spaced from the first surface by the thickness of the stock material, and wherein at least portion of the second layer of material includes a second window that exposes a portion of the second surface; and selectively removing a portion of the stock material exposed at the first or second windows, wherein the portion removed includes less than an entirety of the thickness of the stock material.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 18, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: De Jun Huang, Quan Bang Li
  • Patent number: 10157920
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 10158051
    Abstract: Provided are a process method for bond-packaging an LED using a refined photoconverter, and a refining equipment system. The process method includes the following continuous process flow: roll-shaping of a special-shaped microporous carrier sheet, refining of a semi-cured photoconversion sheet, preparation of a flip chip LED array sheet, forming of LED package elements by roll-bonding, curing of the LED package elements, and cutting of the LED package elements. The present invention has a significant advantage of a refined photoconverter, and especially can meet a requirement of a continuous process flow of bond-packaging an LED using an organic silicone resin photoconverter, so as to enhance the production efficiency and yield of LED packages in industrialized batch production.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: December 18, 2018
    Inventor: Jinhua He
  • Patent number: 10153361
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: December 11, 2018
    Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Qizhi Liu, Anthony K. Stamper
  • Patent number: 10153400
    Abstract: An optoelectronic semiconductor device includes a semiconductor body having a semiconductor region and an active region, wherein the semiconductor region has a covering layer forming a radiation passage surface of the semiconductor body on a side facing away from the active region, the semiconductor region has a current-spreading layer arranged between the covering layer and the active region; the semiconductor device has a contact for the electrical contacting of the semiconductor region; the contact adjoins the current-spreading layer in a terminal area; the contact adjoins the covering layer in a barrier region; and the barrier region runs parallel to the active region and is arranged closer to the active region than the radiation passage surface.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 11, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventor: Guido Weiss
  • Patent number: 10147842
    Abstract: We propose a method of producing a III nitride semiconductor light-emitting device 1 having a p-type semiconductor layer 150 in this order, wherein the p-type semiconductor layer 150 is formed by the steps comprising: an electron blocking layer formation step for forming an electron blocking layer 51 having an Al content higher than that of the barrier layer 42, on the light emitting layer 40; a nitrogen carrier gas supply step for supplying at least a carrier gas containing nitrogen as a main component to a surface of the electron blocking layer 51; and a second p-type contact formation step for forming a second p-type contact layer 55 made of AlyGa1-yN on the electron blocking layer 51 after the nitrogen carrier gas supply step, and wherein the second p-type contact formation step is performed using a carrier gas containing hydrogen as a main component.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: December 4, 2018
    Assignee: DOWA Electronics Materials Co., Ltd.
    Inventors: Takehiko Fujita, Yasuhiro Watanabe
  • Patent number: 10147847
    Abstract: A light emitting device includes an adhesion structure on a metal support structure; a first metal layer on the adhesion structure; a second metal layer comprising Ti on the first metal layer; a GaN-based semiconductor structure on the second metal layer, which includes a first-type semiconductor layer on the metal support structure, an active layer on the first-type semiconductor layer, a second-type semiconductor layer on the active layer, a bottom surface proximate to the metal support structure, a top surface, and a side surface, in which a first thickness of the GaN-based semiconductor structure from the bottom surface to the top surface is less than 5 micrometers; an interface layer comprising Ti; and a contact pad, in which the second metal layer directly contacts the GaN-based semiconductor structure, and a second thickness of the metal support structure is 0.5 times or less than a width of the top surface.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: December 4, 2018
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Cheol Yoo
  • Patent number: 10141325
    Abstract: A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: November 27, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Yuki Yamamoto, Tomohiro Yamashita
  • Patent number: 10134878
    Abstract: Embodiments of the present disclosure generally relate to methods for forming a TFT having a metal oxide layer. The method may include forming a metal oxide layer and treating the metal oxide layer with a fluorine containing gas or plasma. The fluorine treatment of the metal oxide layer helps fill the oxygen vacancies in the metal oxide channel layer, leading to a more stable TFT and preventing a negative threshold voltage in the TFT.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: November 20, 2018
    Inventors: Hao-Chien Hsu, Dong-Kil Yim, Tae Kyung Won, Xuena Zhang, Won Ho Sung, Rodney Shunleong Lim
  • Patent number: 10115915
    Abstract: A method for forming an organic thin film transistor is provided. An interdigital electrode layer is located on a surface of the insulating substrate. An organic semiconductor layer is formed on a surface of the interdigital electrode layer. An insulating layer is located to cover the organic semiconductor layer. A gate electrode is formed on the insulating layer. A method for forming the organic semiconductor layer is provided. An evaporating source is provided, and the evaporating source and the interdigital electrode layer are spaced from each other. The carbon nanotube film structure is heated to gasify an organic semiconductor material to form the organic semiconductor layer on an interdigital electrode layer surface.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: October 30, 2018
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hao-Ming Wei, Yang Wei, Kai-Li Jiang, Shou-Shan Fan
  • Patent number: 10115726
    Abstract: Techniques disclosed herein, provide a method and fabrication structure for accurately increasing feature density for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts or blocks where specified. A multiline layer is formed of three or more different materials that provide differing etch characteristics. Etch masks, including interwoven etch masks, are used to selectively etch cuts within selected, exposed materials. Structures can then be cut and formed. Forming structures and cuts can be recorded in a memorization layer, which can also be used as an etch mask.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: October 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Hoyoung Kang, Anton J. deVilliers
  • Patent number: 10103058
    Abstract: Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: October 16, 2018
    Assignee: Novellus Systems, Inc.
    Inventors: Anand Chandrashekar, Esther Jeng, Raashina Humayun, Michal Danek, Juwen Gao, Deqi Wang