Abstract: In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.

Abstract: A contact window arranging apparatus and a contact window arranging method thereof are provided. A first contact window arrangement number and a second contact window arrangement number respectively corresponding to a first boundary and a second boundary are determined according to a first preset distance, and a third contact window arrangement number and a fourth contact window arrangement number respectively corresponding to the first boundary and the second boundary are determined according to a second preset distance, so as to select a total contact window arrangement number with more contact windows. Through taking a horizontal center line and a vertical center line of a rectangular area as benchmarks the contact windows are arranged in a manner corresponding to the total contact window arrangement number.

Abstract: A method for generating a pattern of a mask includes obtaining data of a plurality of polygons representing a plurality of pattern elements, grouping polygons which overlap or contact with each other among the plural polygons in one group, not setting an evaluation position for evaluating an image of a pattern of the one group on a line segment of sides which overlap or contact with each other among sides of the polygon of the one group, and setting an evaluation position at a portion except for the line segment, and repeating calculating the image of the pattern of the one group, evaluating the calculated image at the set evaluation position, and correcting the pattern based on a result of the evaluating, and generating the pattern of the mask based on a result of the repeating step.

Abstract: A method and apparatus of a novel full chip edge-based mask three-dimensional (3D) model for performing photolithography simulation with consideration for edge coupling effect is described. The method receives a mask design layout in order to perform mask topography effect modeling. The method generates scaling parameters for edge coupling effects. Each scaling parameter has an associated combination of feature width and space. The sum of feature width and space associated with at least one scaling parameter is less than a minimum pitch. The method applies a thick mask model that includes several edge-based kernels to the mask design layout to create a mask 3D residual. To apply the thick mask model to the mask design layout, the method updates the edge-based kernels with the scaling parameters.

Abstract: A design level compatible with a sidewall image transfer process employs an alternating grid of mandrel-type line tracks and non-mandrel-type line tracks. Target structure design shapes are formed such that all vertices of the target structure design shapes are on the grid. The target structure design shapes are classified as mandrel-type design shapes and non-mandrel-type design shapes depending on the track type of the overlapping line tracks for lengthwise portions. All mandrel-type line tracks and straps of the mandrel-type design shapes less lateral strap regions of the non-mandrel-type design shapes collectively form mandrel design shapes, which can be employed to generate a first lithographic mask. Sidewall design shapes are generated from the mandrel design shapes. Blocking shapes for a second lithographic mask can be generated by selecting all areas that are not included in the target structure design shapes or the sidewall design shapes.

Abstract: Methods and apparatuses for modifying a Gerber-compliant data structure that is representative of an existing printed circuit board (PCB) layout are described. This may include obtaining a Gerber-compliant data structure which includes layout information describing the physical layout of a PCB, obtaining modification information representing a modification to the physical layout of the PCB, and automatically modifying the Gerber-compliant data structure to seamlessly incorporate the modification information to create a new electrical connectivity structure for the Gerber-compliant data structure.

Abstract: A method for printed circuit board design of temperature sensitive components includes a scrub tool receiving a list of part numbers for electronic components of a printed circuit board assembly (“PCBA”). The scrub tool sends one or more queries for finding temperature and time limits of the electronic components to a database. A mapping tool receives a selection of one or more part numbers responsive to the one or more queries, wherein the selection is responsive to the temperature and time limits. The mapping tool sends a data structure to a physical design tool which is configured with physical design data for generating a graphic representation of the PCBA. The data structure from the mapping tool provides the received selection of one or more part numbers and configures the physical design tool to highlight components having part numbers of the selection on the PCBA graphic representation.

Abstract: A chargeable energy store includes a chargeable electrical accumulator, an interface for connecting the accumulator to a device for the exchange of energy and a control unit for controlling the energy exchange of the accumulator. The control unit includes a supply voltage terminal, which is connected to the accumulator when a device is connected to the interface for the exchange of energy, and which is otherwise disconnected from the accumulator.

Abstract: The present disclosure relates to a method of generating a scaled integrated chip design by scaling a FEOL and a BEOL of an original IC design at different scaling ratios, and an associated apparatus. In some embodiments, the method is performed by forming an original integrated chip (IC) design that is a graphical representation of an integrated chip. The original IC design has a front-end-of-the-line (FEOL) section, a back-end-of-the-line (BEOL) section, and a middle-of-the-line (MOL) section that is disposed between the FEOL and BEOL sections. A scaled integrated chip design is formed by scaling (i.e., shrinking) the FEOL section and the BEOL section of the original integrated chip design at different scaling ratios, and by scaling different design layers within the MOL section at different scaling ratios to avoid misalignment errors between the FEOL section and the BEOL section.

Abstract: System and methods for OPC model accuracy and disposition using quad matrix are presented. A method includes obtaining wafer data from a calibration test pattern. The method also classifies the wafer data into four quadrants of a quad matrix. The method further utilizes at least one of the four quadrants to quantify OPC model accuracy.

Abstract: In one aspect of an embodiment, a method implemented on a data processing system for circuit design, includes identifying one or more first portions of a design of a circuit, each of the one or more first portions containing a set of elements interconnected via timing nets and generating weights for the timing critical nets, the weights being generated after identifying the one or more first portions and executing a placer algorithm which uses the weights for the timing critical nets to place the set of elements on a representation of the design. In this method, in one embodiment, the weights for the timing critical nets can be generated to have values that differ from weights for non-critical nets. The placer algorithm can be any one of a variety of conventional placer algorithms such as a weighted wire length driven placer algorithm or a force directed timing driven placer algorithm or a min-cut placer algorithm.

Abstract: Recycling energy in a clock distribution network is provided. A method includes creating a resonant clocking circuit including a clock grid. The method further includes providing resonant structures distributed in the clock grid. The method further includes providing switches that control the resonant structures to switch between a non-resonant mode and a resonant mode. The method further includes determining a switch size that minimizes power consumption of the resonant clocking circuit by iteratively increasing sizes of the switches and, for each iterative increase in size, determining power consumed by the resonant clocking circuit.

Abstract: A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.

Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for voltage-related analysis of layout design data. According to embodiments of the disclosed technology, voltage association data objects are generated for drawn layers in a net of a layout design and voltage values or ranges of voltage values associated with the net are collected. The voltage values or ranges of voltage values are then associated with the voltage association data objects. A voltage-related analysis may be performed by searching the voltage association data objects according to a predetermined criterion.

Abstract: A computer-implemented method and information handling system manage a rate of decreasing full capacity of a rechargeable battery by using a projected/target rate of decreasing charge capacity for the battery. The method includes determining an actual rate of decreasing charge capacity of the battery, comparing the actual rate of decreasing charge capacity to the projected/target rate of decreasing charge capacity to determine whether the actual rate of decreasing charge capacity is greater than the projected rate of decreasing charge capacity, and if the actual rate of decreasing charge capacity is greater than the projected/target rate of decreasing charge capacity, modifying one or more variable parameters to slow down the actual rate of decreasing charge capacity of the battery such that the actual rate of decreasing charge capacity remains within a range of the projected/target rate of decreasing charge capacity, and charging and discharging the battery using the modified parameters.

Abstract: A method and apparatus for an efficient optical proximity correction (OPC) repair flow is disclosed. Embodiments may include receiving an input data stream of an integrated circuit (IC) design layout, performing one or more iterations of an OPC step and a layout polishing step on the input data stream, and performing a smart enhancement step if an output of a last iteration of the OPC step fails to satisfy one or more layout criteria and if a number of the one or more iterations satisfies a threshold value. Additional embodiments may include performing a pattern insertion process cross-linked with the OPC step, the pattern insertion process being a base optical rule check (ORC) process.

Abstract: A charging apparatus and an electric vehicle including the same are disclosed. The charging apparatus includes a rectifier to rectify input alternating current (AC) power in a charging mode, an interleaved buck-boost converter to convert the rectified power into direct current (DC) power to supply the converted DC power to a battery, the interleaved buck-boost converter including a plurality of buck-boost converters, and a converter controller to control the interleaved buck-boost converter, wherein a first buck-boost converter of the interleaved buck-boost converter includes a first buck switching element connected to the rectifier, a first boost switching element, an inductor connected between the first buck switching element and the first boost switching element, a first diode connected in parallel between the first buck switching element and the inductor, and a second diode connected between the first boost switching element and an output of the interleaved buck-boost converter.

Abstract: The present invention provides a novel method for charging silver-zinc rechargeable batteries and an apparatus for practicing the charging method. The recharging apparatus includes recharging management circuitry; and one or more of a silver-zinc cell, a host device or a charging base that includes the recharging management circuitry. The recharging management circuitry provides means for regulating recharging of the silver-zinc cell, diagnostics for evaluating battery function, and safety measures that prevent damage to the apparatus caused by charging batteries composed of materials that are not suited for the charging method (e.g., non-silver-zinc batteries).

Abstract: Optical simulation can be performed employing a calibrated printing model, in which a unique phase transmission value is assigned to each type of sub-resolution assist features (SRAFs). The printing model can be calibrated employing a mask including multiple test patterns. Each test pattern is defined by a combination of a main feature, at least one SRAF applied to the main feature, and the geometrical relationship between the main feature and the at least one SRAF. Generation of the phase transmission values for each SRAF can be performed by fitting a printing model employing phase shift values and/or transmission values for SRAFs with measured printed feature dimensions as a function of defocus and/or with measured SRAF printing behavior on a printed photoresist layer. A properly calibrated printing model can predict the printed feature dimensions, shift in the best focus, and presence or absence of printed SRAFs.

Abstract: Various implementations of a method, system, and computer program product for executing timing analysis of an asynchronous clock domain crossing are disclosed. In one embodiment, a signal group and a corresponding timing specification are determined for one or more signals of an electronic design. For each of the signals, a clock associated with the signal is renamed based, at least in part, on the signal group associated with the signal. The asynchronous clock domain between a transmit domain and a receive domain is identified in the electronic design based, at least in part, on identifying a signal path associated with one or more renamed clocks that is asynchronous to a clock associated with the receive domain. For each of the one or more renamed clocks, timing analysis is executed across one or more signals associated with the renamed clock at the asynchronous clock domain crossing.