Abstract: Methods and systems for implementing track pattern for electronic designs are disclosed. The method identifies a first track in a design and viable implementing options for the first track. When adding a second track to the track pattern, the method determines whether the second track corresponds to the viable implementing options for the track. The second track is inserted to the track pattern and situated immediately adjacent to the first track if the second track is determined to correspond to a viable implementing option for the first track. One or more intermediate tracks may be inserted immediately adjacent to the first track before inserting the second track to produce a legal track pattern. Tracks may be removed from a track pattern. One or more intermediate tracks may be inserted into the space occupied by a track being removed to ensure track pattern's compliance with design rules after the track removal.

Abstract: A method for simulating a power consumption associated with a circuit. Once a netlist describing the circuit and an input stimulus for the netlist are obtained, the netlist is partitioned into multiple circuit blocks. Circuit logic models (CLMs) implemented in a hardware description language (HDL) are then obtained for the multiple circuit blocks and a logic netlist is generated from the multiple CLMs. A power vector for a CLM corresponding to a circuit block is calculated using a logic simulator inputting the logic netlist and the input stimulus. Further, a power consumption value is calculated for the circuit block using a circuit simulator and the power vector. The power consumption associated with the circuit is calculated based on the power consumption values for various circuit blocks.

Abstract: A method is disclosed that includes the operation below. Vertices in a conflict graph are sorted into a first clique and a second clique, in which the conflict graph corresponds to a layout of a circuit. A first vertex of the vertices is merged with a second vertex of the vertices, to generate a reduced graph, in which the first clique excludes the second vertex, and the second clique excludes the first vertex. A first color pattern of a plurality of color patterns is assigned to a first pattern, corresponding to the first vertex, and a second pattern, corresponding to the second vertex, in the layout according to the reduced graph.

Abstract: Systems and methods are disclosed herein to provide improved placement of components in programmable logic devices (PLDs). In one example, a computer-implemented method includes receiving a design identifying operations to be performed by a PLD. The method also includes determining a layout comprising positions of components of the PLD configured to perform the operations. The method also includes performing a timing analysis on the layout. The method also includes selectively adjusting the positions of the components using the timing analysis. Related systems and non-transitory machine-readable mediums are also provided.

Abstract: A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.

Abstract: A method, system, and computer program product for enhancing integrated circuit noise performance. The method is for arranging target wires in a target region, the method including: for each wire in the target wires, obtaining a signal jump interval with respect to each of the other wires in the target wires, wherein the signal jump interval of one wire with respect to a further wire is a time interval between occurrence of signal jump on the one wire and occurrence of signal jump on the further wire; calculating a corresponding time influence factor based on the signal jump interval, wherein the time influence factor is a decreasing function of the signal jump interval; and arranging the target wires in the target region based on the time influence factor. Coupling noise between wires may be reduced according to the technical solution of an embodiment of the present invention.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Abstract: One aspect includes identifying via groups that each includes a ratio of a plurality of signal vias to one ground via based on a design file defining a layout of a multi-layer circuit board. A genetic via placement solver iteratively evaluates potential placement solutions that adjust a placement of one or more of the signal vias until at least one solution is identified that meets one or more placement criteria of the signal vias. The genetic via placement solver performs a mutation and recombination of one or more solutions that do not meet the one or more placement criteria and re-evaluates the one or more solutions that do not meet the one or more placement criteria. The design file is modified to include at least one shifted signal via position based on identifying the at least one solution that meets the one or more placement criteria.

Abstract: In an approach for determining voltage and frequency pairs, the computer identifies an integrated circuit design. The computer identifies a timing model associated with the identified integrated circuit design. The computer identifies at least a nominal voltage, a nominal clock signal, and a voltage range associated with the integrated circuit design. The computer receives a number n that defines the number of at least one alternate voltage within the voltage range. The computer analyzes the identified integrated circuit based on the received number n for each number n for at least one alternate voltage within the voltage range. The computer calculates a nominal slack. The computer calculates one or more clock periods based on the calculated nominal slack. The computer provides a report based on the calculated one or more clock periods.

Abstract: A method of filtering overlay data by field is provided in the present invention. The method includes the following steps. A minimum number of measure points per field on a semiconductor substrate is decided. Field data filtering rules are set. Overlay raw data is inputted. A raw data filtration is performed to the overlay raw data by field according to the field data filtering rules. Modified exposure parameters are generated for each field according to overlay data of remaining measure points per field after the raw data filtration when the number of the remaining measure points per field is larger than or equal to the minimum number of the measure points per field. Accordingly, the modified exposure parameters will be more effective in reducing the overlay error because more outliers may be filtered out before generating the modified exposure parameters.

Abstract: A method of determining colorability of a layer of a semiconductor device includes iteratively decomposing a conflict graph to remove all nodes having fewer links than a threshold number of links. The method further includes determining whether the decomposed conflict graph is a simplified graph. The method further includes partitioning, using a specific purpose processing device, the decomposed conflict graph if the decomposed conflict graph is not a simplified graph. The method further includes determining whether the decomposed conflict graph is colorable based on a number of masks used to pattern the layer of the semiconductor device if the decomposed conflict graph is a simplified graph. The method further includes flagging violations if the decomposed conflict graph is not colorable.

Abstract: In a compression scan, the number of test steps is reduced without reducing a defection efficiency. A semiconductor apparatus includes one or more scan chains each including one or more MMSFFs being serially connected and combinational circuits and can switch between a scan shift operation and a capture operation. The MMSFF includes an MUX that selects one of an external input test signal which is externally input and a shift test signal which is input via the MMSFF in a preceding stage in the same scan chain, and an FF that outputs one of the external input test signal and the shift test signal which has been selected by the MUX.

Abstract: Embodiments include methods, processing systems and computer program products for extracting via capacitance. Aspects include placing various shapes of target nets of an IC into a Cshapes collection and a CshapesVia collection, processing the shapes in these collections and placing the processed shapes into a Ctile collection and a CtilesVia collection, and extracting via capacitance of the target nets through each of Cshapes, CshapesVia, Ctiles, and CtilesVia collections. In exemplary embodiments, the processing operation includes: reducing the complexity of the shapes in the shape collections, removing all overhang shapes, and all overlapped shapes from the shape collections, and unioning the shapes in the Cshapes collection and the CshapesVia collection, respectively.

Abstract: Battery charging methods and systems for devices that have rechargeable batteries provide an efficient way to know when to charge a device's battery, and when to switch between the device's battery and an external power source as the device's power source. The methods and systems receive signals associated with an external information service including instructions to conduct processing, access thresholds for a plurality of power rates, obtain information about when different power rates are in effect and, after determining a charge level associated with a battery, compare the threshold of the current power rate to the device's battery's charge level. Based on such a comparison, the methods and systems can determine whether the battery should be charged and whether the device's battery or an external power source should be used as the device's power source.

Abstract: A timing-matching method, executed by a timing analyzer, that includes computing a slew or load of a cell, determining whether the slew or load exists in an extrapolation region of a standard cell look-up table, and swapping the cell with a virtual standard cell of a virtual standard cell look-up table when the slew or load exists in the extrapolation region.

Abstract: Methods for selecting the best measurement sites for OPC model calibration are disclosed. Embodiments include selecting a predetermined number, n, of structures representing an IC design layout eligible for SEM measurement; specifying an image parameter space of image parameters for the n structures; optimizing a redundancy in the image parameter space of measurement sites for the n structures; and calibrating an OPC model for the IC design layout based on the optimized redundancy.

Abstract: Described is a method for automatically determining proposed standard cell design conformance based upon template constraints.

Abstract: A system for dynamic circuit board design, preferably including a library of modular circuits and a merge tool. A method for merging modular circuitry into a unified electronics module, preferably including: receiving a circuit board layout, the circuit board layout preferably including a set of modular circuits arranged on a virtual carrier board; converting the circuit board layout into a virtual circuit representation; applying transformations to the virtual circuit representation; and generating a unified circuit board design based on the transformed virtual circuit representation.