Patents Examined by Brendan Lillis
  • Patent number: 9304686
    Abstract: A data storage device is disclosed. In one embodiment, the data storage device comprises a flash memory and a controller. The flash memory comprises a plurality of blocks, wherein each block comprises a plurality of pages, and each page comprises a plurality of data trimming units which is a smallest unit for data modification. After a data trimming process has been performed on an address range of the flash memory, the controller determines a last page corresponding to an ending address of the address range, determines whether data values stored in the last page with addresses subsequent to the ending address are all equal to a specific data pattern, and sets the value of a trimming flag corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending address are all equal to the specific data pattern.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 5, 2016
    Assignee: SILICON MOTION, INC.
    Inventor: Chang-Kai Cheng
  • Patent number: 9213612
    Abstract: In a system and method for a storage area network (SAN), a first controller receives a write request for a SAN and communicates with a first nested storage array module (NSAM), the first NSAM manages storage of data onto a shelf and presents the shelf as a logical unit, a buffer stores a portion of a write request from the first controller and aggregates data from the write request for the shelf, from a shelf with a second NSAM, the second NSAM provides a portion of data from the buffer to a third NSAM, the third NSAM manages storage of the portion of data from the buffer to a physical storage unit, and a second controller coupled to the first controller handles requests for the SAN in response to a failure of the first controller.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: December 15, 2015
    Assignee: CISCO TECHNOLOGY, INC.
    Inventor: James Candelaria
  • Patent number: 9195604
    Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: November 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Siamack Nemazie, Farshid Tabrizi, Berhanu Iman, Ruchir Shah, William E. Benson, Michael George
  • Patent number: 9176824
    Abstract: The remote access to backed-up user data techniques include a method, a system, and/or an apparatus. In some embodiments of these techniques, the method includes receiving a request from a user interface to view a backed-up data. The method further includes retrieving a cache entry corresponding to the backed-up data from a cache, displaying contents of the backed-up data in the user interface using the retrieved cache entry, and validating the cache entry after displaying the contents of the backed-up data.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: November 3, 2015
    Assignee: Carbonite, Inc.
    Inventors: Gordon T. Henriksen, Jeffry C. Flowers
  • Patent number: 9135115
    Abstract: A method begins by a processing module of a dispersed storage network (DSN) receiving data in a redundant array of independent disks (RAID) format and converting from the RAID format to an original format of the data. The method continues with the processing module dispersed storage error encoding a data segment of the data in the original format to produce a set of encoded data slices, where a set of encoded data slices includes a decode threshold sub-set of encoded data slices and an error correcting sub-set of encoded data slices. The method continues with the processing module converting the decode threshold sub-set of encoded data slices into a RAID formatted data segment, storing the RAID formatted data segment in RAID memory, and storing at least the error correcting sub-set of encoded data slices in DSN memory.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: September 15, 2015
    Assignee: Cleversafe, Inc.
    Inventors: Gary W. Grube, Jason K. Resch
  • Patent number: 9104594
    Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: August 11, 2015
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Ernest S. Cohen, John Te-Jui Sheu, Landy Wang, Matthew D. Hendel, Rene Antonio Vega, Sharvil A. Nanavati
  • Patent number: 9021214
    Abstract: According to a storage system of a prior art adopting a cluster structure, various types of large-capacity memories were arranged to enhance the access performance, so that the system required a dedicated control circuit, and there was difficulty in realizing cost reduction and improvement of access performance simultaneously. In order to solve the problems, the present invention provides a storage system in which a group of memories is integrated to MPU memories directly coupled to MPUs in respective controller units, wherein each MPU memory is divided into a duplication information area and a non-duplication information area, and attribute information for controlling accesses thereto are provided.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 28, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Yuki Sakashita, Shintaro Kudo, Yusuke Nonaka
  • Patent number: 9003158
    Abstract: A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: April 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Quyen Pho
  • Patent number: 8966176
    Abstract: Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: February 24, 2015
    Assignee: SanDisk IL Ltd.
    Inventors: Yacov Duzly, Guy Freikorn, Nir Perry, Alon Marcu
  • Patent number: 8949559
    Abstract: It is an object to use a storage region in an efficient manner and maintain a performance of a storage system. A volume group GR11 includes reference volumes 1411, 1413, and 1415 and source volumes 1412, 1414, 1416, and 1417 that derive from the reference volumes. Each of the volumes stores only the difference data from a volume that is a parent thereof. A volume that is a cause of a problem is moved or copied from a pool of the moment 1410 to other pool 1420. A configuration of a volume group is modified.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: February 3, 2015
    Assignee: Hitachi, Ltd.
    Inventors: Toru Tanaka, Noriko Nakajima, Takashi Amano, Yasunori Kaneda
  • Patent number: 8938002
    Abstract: A data processing apparatus, a data processing method, and a program that are configured to prevent (or lower) the increase in scale and cost of the apparatus. A read/write control portion executes read/write control in which slots subject to extraction of two or more slots in one frame that is a collection of two or more slots each of which is a unit of error correction coding are written to a ring buffer and the slots subject to extraction in one frame written to the ring buffer are read within the unit time. When slots subject to extraction are changed, an output portion executes output processing in which dummy data outputted from a dummy data output portion are outputted with a timing immediately before a change start frame that is a frame from which the change of slots subject to extraction is started and, slots subject to extraction read from the ring buffer are outputted for frames subsequent to the change start frame.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: January 20, 2015
    Assignee: Sony Corporation
    Inventors: Hideyuki Matsumoto, Yuichi Mizutani
  • Patent number: 8938604
    Abstract: The present disclosure provides a storage system for data read and write. One embodiment of the storage system includes an origination device that is configured to receive a request for a logical block addressing-based operation on a volume, convert the logical block addressing-based operation request into a key addressing-based operation request carrying a key corresponding to data to be operated, and send the key addressing-based operation request to a routing library; the routing library is configured to receive the key addressing-based operation request, hash the key corresponding to the data to be operated, determine that a storage node taking charge of a hash region in which the hashed key is located is the master storage node, send the key addressing-based operation request to the master storage node of the data to be operated.
    Type: Grant
    Filed: December 5, 2012
    Date of Patent: January 20, 2015
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xian Liu, Daohui Wang, Deping Yang
  • Patent number: 8904127
    Abstract: A method of performing a data write on a storage device comprises instructing a device driver for the device to perform a write to the storage device, registering the device driver as a transaction participant with a transaction co-ordinator, executing a flashcopy of the storage device, performing the write on the storage device, and performing a two-phase commit between device driver and transaction co-ordinator. Preferably, the method comprises receiving an instruction to perform a rollback, and reversing the data write according to the flashcopy. In a further refinement, a method of scheduling a flashcopy of a storage device comprises receiving an instruction to perform a flashcopy, ascertaining the current transaction in relation to the device, registering the device driver for the device as a transaction participant in the current transaction with a transaction co-ordinator, receiving a transaction complete indication from the co-ordinator, and executing the flashcopy for the device.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. Hutchison, Cameron J. McAllister, Lucy A. Harris, Bruce J. Smith
  • Patent number: 8904130
    Abstract: A method of performing a data write on a storage device comprises instructing a device driver for the device to perform a write to the storage device, registering the device driver as a transaction participant with a transaction co-ordinator, executing a flashcopy of the storage device, performing the write on the storage device, and performing a two-phase commit between device driver and transaction co-ordinator. Preferably, the method comprises receiving an instruction to perform a rollback, and reversing the data write according to the flashcopy. In a further refinement, a method of scheduling a flashcopy of a storage device comprises receiving an instruction to perform a flashcopy, ascertaining the current transaction in relation to the device, registering the device driver for the device as a transaction participant in the current transaction with a transaction co-ordinator, receiving a transaction complete indication from the co-ordinator, and executing the flashcopy for the device.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. Hutchison, Cameron J. McAllister, Lucy A. Harris, Bruce J. Smith
  • Patent number: 8892847
    Abstract: The storage apparatus comprises a storage unit storing data read/written by the host apparatus, and a control unit controlling writing of the data to the storage unit. The control unit configures one or more pools from the storage unit and divides one of the pools into first pages having an area of a first size and divides the first pages into second pages having the second area, and manages the pages, manages a data storage area of a first volume storing the data by using the first-size area and manages a data storage area of a second volume storing the data by using the second-size area, assigns the first page to the data storage area of the first volume, and assigns the first page in units of the second volume and assigns the second page obtained by dividing the first page to the data storage area of the second volume.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: November 18, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Miho Imazaki, Yusuke Nonaka
  • Patent number: 8886911
    Abstract: Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a size of a memory cache in the memory array responsive to the available memory space.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Siamack Nemazie, Farshid Tabrizi, Berhanu Iman, Ruchir Shah, William E. Benson, Michael George
  • Patent number: 8868860
    Abstract: In one aspect of the present description, handling multiple backup processes comprises detecting that a defined storage volume is present in a first cascade of storage volumes; detecting that the defined storage volume is present in a second cascade of storage volumes; receiving a data write for a last storage volume in the first cascade of storage volumes; and performing a cleaning data write on the defined storage volume in the second cascade of storage volumes, wherein the cleaning data write corresponds to the received data write. Other aspects may be utilized, depending upon the particular application.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventor: Christopher B. Beeken
  • Patent number: 8862825
    Abstract: A processor and an operating method are described. By diversifying an L1 memory being accessed, based on an execution mode of the processor, an operating performance of the processor may be enhanced. By disposing a local/stack section in a system dynamic random access memory (DRAM) located external to the processor, a size of a scratch pad memory may be reduced without deteriorating a performance. While a core of the processor is performing in a very long instruction word (VLIW) mode, the core may data-access a cache memory and thus, a bottleneck may not occur with respect to the scratch pad memory even though a memory access occurs with respect to the scratch pad memory by an external component.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 14, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwon Taek Kwon
  • Patent number: 8856487
    Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Emanuele Confalonieri, Corrado Villa
  • Patent number: 8856472
    Abstract: In one aspect of the present description, handling multiple backup processes comprises detecting that a defined storage volume is present in a first cascade of storage volumes; detecting that the defined storage volume is present in a second cascade of storage volumes; receiving a data write for a last storage volume in the first cascade of storage volumes; and performing a cleaning data write on the defined storage volume in the second cascade of storage volumes, wherein the cleaning data write corresponds to the received data write. Other aspects may be utilized, depending upon the particular application.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventor: Christopher B.E. Beeken