Abstract: Systems, devices, memory controllers, and methods for initializing memory are described. Initializing memory can include configuring memory devices in parallel. The memory devices can receive a shared enable signal. A unique volume address can be assigned to each of the memory devices.

Abstract: A method begins by a processing module determining whether to convert data between a redundant array of independent disks (RAID) format and a dispersed storage network (DSN) format. The method continues with the processing module retrieving the data from a RAID memory to produce retrieved RAID data when the data is to be converted from the RAID format to the DSN format. The method continues with the processing module converting stripe-block data of the retrieved RAID data into a plurality of sets of encoded data slices and outputting the plurality of sets of encoded data slices to at least one of the RAID memory and a DSN memory for storage therein.

Abstract: A method of maintaining and updating a logical-to-physical (LtoP) table in a storage device including a processor, a volatile memory, and a non-volatile memory, the storage device being in communication with a host, the method including receiving, by the processor, data for storing at a physical address in the non-volatile memory, the data being associated with a logical address of the host, storing, by the processor, the physical address in a first LtoP zone of a plurality of LtoP zones of the LtoP table, the LtoP table being stored in the volatile memory, adding, by the processor, the first LtoP zone to a list of modified zones, and storing, by the processor, a second LtoP zone of the plurality of LtoP zones in the non-volatile memory when a size of the list of modified zones exceeds a threshold.

Abstract: A computer system in which one or more host computers 30 having a FC (Fiber Channel) node port and one or more storage apparatuses 40 having a FC node port are coupled via a FC fabric. The storage apparatus acquires first information related to access control for controlling access to a relevant storage apparatus by the host computer. The storage apparatus, based on the first information, creates second information for defining the host computer that is able to access the relevant storage apparatus, and registers this second information in the fabric.

Abstract: A storage device includes first and second buffers. A request to write a new record from a host is received. A hash value (new S) of the new record is calculated. The hash value (new S) of the new record is checked to determine if the hash value exists in a second buffer. If the new S exists in the second buffer, the new record is compared with a record stored in the second buffer corresponding to the new S to check if the new record and the stored record in the second buffer match each other. If the new record and the stored record match each other, a pointer (a record number) is written as write data of the new record to the recording medium. The pointer points to the record already stored in any one of a recording medium and the second buffer.

Abstract: A data processing system 2 including processing circuitry 4 operating in either a first mode or a second mode. Page table data 30 including access control bits 40, 42, is used to control permissions for memory access to memory pages. In the first mode, the access control bits include at least one instance of a redundant encoding. In the second mode, the redundant encoding is removed to provide more efficient use of the access control bit encoding space.

Abstract: A memory controller is for controlling access to a memory device of the type having a non-uniform access timing characteristic. An interface receives transactions issued from at least one transaction source and a buffer temporarily stores as pending transactions those transactions received by the interface that have not yet been issued to the memory device. The buffer maintains a plurality of ordered lists (having a number of entries) for the stored pending transactions, including at least one priority based ordered list and at least one access timing ordered list. Each entry being associated with one of the pending transactions, and ordered within its priority based ordered list based on the priority indication of the associated pending transaction. Arbitration circuitry performs an arbitration operation during which the plurality of ordered lists are referenced so as to select a winning transaction to be issued to the memory device.

Abstract: One of a backup apparatus and a storage system performs control to store backup data in a storage system which belongs to an organization and/or location different from an organization and/or location to which a storage-target storage system for original data belongs, based on information (P) and/or (Q) below: (P) information relating to original data, and information relating to backup data, which is a copy of the original data; (Q) information indicating an organization and/or location to which each storage system belongs.

Abstract: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.

Abstract: Various mechanisms are disclosed for improving the operational efficiency of a virtual translation look-aside buffer (TLB) in a virtual machine environment. For example, one mechanism fills in entries in a shadow page table (SPT) and additionally, speculatively fills in other entries in the SPT based on various heuristics. Another mechanism allows virtual TLBs (translation look-aside buffers) to cache partial walks in a guest page table tree. Still another mechanism allows for dynamic resizing of the virtual TLB to optimize for run-time characteristics of active workloads. Still another mechanism allows virtual machine monitors (VMMs) to support legacy and enlightened modes of virtual TLB operation. Finally, another mechanism allows the VMM to remove only the stale entries in SPTs when linking or switching address spaces. All these mechanisms, together or in part, increase the operational efficiency of the virtual TLB.

Abstract: One embodiment provides a computer system and data backup method which enable improvements in the response performance of a storage apparatus to a write request from a host apparatus. In a case where, during execution of same intra-enclosure copy processing, a primary storage apparatus receives a write request in which the data write destination is a storage area in a target range for the same intra-enclosure copy processing in a first primary volume in the primary storage apparatus, the primary storage apparatus transmits an advance notification storing an address of a storage area in a secondary storage apparatus which corresponds to the data write destination storage area designated in the write request to the secondary storage apparatus such that an on-demand copy is executed based on the advance notification in the secondary storage apparatus.