Patents Examined by Brett Feeney
  • Patent number: 8993372
    Abstract: Exemplary embodiments of a method for producing a semiconductor component having a polycrystalline semiconductor body region are disclosed, wherein the polycrystalline semiconductor body region is produced between the first and second surfaces of the semiconductor body in a semiconductor component section, wherein an electromagnetic radiation having a wavelength of at least 1064 nm is introduced into the semiconductor body in a manner focused onto a position in the semiconductor component section of the semiconductor body and wherein the power density of the radiation at the position is less than 1×108 W/cm2.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: March 31, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Manfred Schneegans, Carsten Ahrens, Adolf Koller, Gerald Lackner, Anton Mauder, Hans-Joachim Schulze
  • Patent number: 8987826
    Abstract: A method of manufacturing a semiconductor device comprises forming an interlayer insulating film on a semiconductor substrate, the interlayer insulating film including a trench, forming a work function metal layer in the trench, forming an insulating film on the work function metal layer, forming a sacrificial film on the insulating film and filling the trench, forming a sacrificial film pattern with a top surface disposed in the trench by etching the sacrificial film, forming an insulating film pattern by selectively etching a portion of the insulating film which is formed higher than the sacrificial film pattern, and forming a work function metal pattern with a top surface disposed in the trench by selectively etching a portion of the work function metal layer which is formed higher than the insulating film pattern.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: March 24, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Youn Kim
  • Patent number: 8987054
    Abstract: In one embodiment, methods for making semiconductor devices are disclosed.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventor: Darrell Truhitte
  • Patent number: 8987087
    Abstract: A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: March 24, 2015
    Assignee: Sandisk Technologies Inc.
    Inventors: Henry Chien, Donovan Lee, Vinod R. Purayath, Yuan Zhang, James K. Kai, George Matamis
  • Patent number: 8987865
    Abstract: A resistor structure incorporated into a resistive switching memory cell or device to form memory devices with improved device performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory device. A method is also provided for making such memory device. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory device, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory device. The incorporation of the resistor structure is very useful in obtaining desirable levels of device switching currents that meet the switching specification of various types of memory devices. The memory devices may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: March 24, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Dipankar Pramanik, Tony P. Chiang, Mankoo Lee
  • Patent number: 8975184
    Abstract: Methods of filling features with low-resistivity tungsten layers having good fill without use of a nucleation layer are provided. In certain embodiments, the methods involve an optional treatment process prior to chemical vapor deposition of tungsten in the presence of a high partial pressure of hydrogen. According to various embodiments, the treatment process can involve a soaking step or a plasma treatment step. The resulting tungsten layer reduces overall contact resistance in advanced tungsten technology due to elimination of the conventional tungsten nucleation layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Novellus Systems, Inc.
    Inventors: Feng Chen, Tsung-Han Yang, Juwen Gao, Michal Danek
  • Patent number: 8975727
    Abstract: A resistor structure incorporated into a resistive switching memory cell with improved performance and lifetime is provided. The resistor structure may be a two-terminal structure designed to reduce the maximum current flowing through a memory cell. A method is also provided for making such a memory cell. The method includes depositing a resistor structure and depositing a variable resistance layer of a resistive switching memory cell of the memory cell, where the resistor structure is disposed in series with the variable resistance layer to limit the switching current of the memory cell. The incorporation of the resistor structure is very useful in obtaining desirable levels of switching currents that meet the switching specification of various types of memory cells. The memory cells may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 10, 2015
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Dipankar Pramanik, Takeshi Yamaguchi
  • Patent number: 8975164
    Abstract: The present invention provides a method of manufacturing a semiconductor device. The method at least comprises the following steps. First, the semiconductor device, which comprises a gate, a gate dielectric layer, an active layer, a source and a drain, is manufactured. However, the semiconductor device has a plurality of defects, and the active layer is a metal oxide thin film. After annealing the semiconductor device, it will be transferred into a chamber. A final step of injecting a supercritical fluid carried with a co-solvent into the chamber is then performed to modify the abovementioned defects.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: March 10, 2015
    Assignee: National Chiao Tung University
    Inventors: Po-Tsun Liu, Wei-Ya Wang, Li-Feng Teng
  • Patent number: 8975166
    Abstract: Methods and apparatus for generating and delivering atomic hydrogen to the growth front during the deposition of a III-V film are provided. The apparatus adapts HWCVD technology to a system wherein the Group III precursor and the Group V precursor are delivered to the surface in isolated processing environments within the system. Multiple HWCVD units may be incorporated so that the atomic hydrogen parameters may be varied in a combinatorial manner for the development of III-V films.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: March 10, 2015
    Assignee: Intermolecular, Inc.
    Inventors: Thai Cheng Chua, Timothy Joseph Franklin, Philip A. Kraus
  • Patent number: 8969193
    Abstract: A semiconductor substrate (1) is provided on a main surface (14) with an intermetal dielectric (4) including metal planes (5) and on an opposite rear surface (15) with an insulation layer (2) and an electrically conductive connection pad (7). An etch stop layer (6) is applied on the intermetal dielectric to prevent a removal of the intermetal dielectric above the metal planes during subsequent method steps. An opening (9) having a side wall (3) and a bottom (13) is formed from the main surface through the substrate above the connection pad. A side wall spacer (10) is formed on the side wall by a production and subsequent partial removal of a dielectric layer (11). The insulation layer is removed from the bottom to uncover an area of the connection pad. A metal layer is applied in the opening and is provided for an interconnect through the substrate.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: March 3, 2015
    Assignee: ams AG
    Inventors: Jochen Kraft, Franz Schrank, Martin Schrems
  • Patent number: 8969199
    Abstract: One illustrative method disclosed herein includes, among other things, patterning a hard mask layer using three patterned photoresist etch masks, wherein a first feature corresponding to a portion, but not all, of a cross-coupling gate contact structure is present in a first of the three patterned photoresist etch masks and a second feature corresponding to a portion, but not all, of the cross-coupling gate contact structure is present in a second or a third of the three patterned photoresist etch masks, patterning a layer of insulating material using the patterned hard mask layer as an etch mask, and forming a cross-coupling gate contact structure in a trench in the layer of insulating material.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Globalfoundries Inc.
    Inventors: Lei Yuan, Jason Eugene Stephens, Li Yang, Soo Han Choi
  • Patent number: 8927318
    Abstract: A method cleaving a semiconductor material that includes providing a germanium substrate having a germanium and tin alloy layer is present therein. A stressor layer is deposited on a surface of the germanium substrate. A stress from the stressor layer is applied to the germanium substrate, in which the stress cleaves the germanium substrate to provide a cleaved surface. The cleaved surface of the germanium substrate is then selective to the germanium and tin alloy layer of the germanium substrate. In another embodiment, the germanium and tin alloy layer may function as a fracture plane during a spalling method.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Devendra K. Sadana, Davood Shahrjerdi
  • Patent number: 8904391
    Abstract: A computer implemented method, data processing system, and computer program product for dynamically binding business process activities to human entities at deployment time. Identification information about a staff activity in a business process is received from a process server at an access control system external to the process server. Responsive to initiation of the business process, the staff activity is resolved at the access control system at runtime by assigning the staff activity to a user based on an access policy of the access control system to form a staff activity assignment. The staff activity assignment is communicated from the access control system to the process server. The process allows the development of the business process to be entirely decoupled from staff activity resolution at runtime.
    Type: Grant
    Filed: April 23, 2007
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Messaoud B. Benantar, Hari Haranath Madduri
  • Patent number: 8886553
    Abstract: In a method of a technology for visual workflow process notation and layout, a workflow process graphical user interface is generated. A plurality of activity nodes is arranged along a workflow path, with each activity node representing a work activity. The activity nodes are arranged on the workflow path in representation of an order of performance of work activities within the process of performing work. A material flow path is arranged adjacent to the workflow path. The material flow path is representative of a flow of a material through the work activities associated with the plurality of activity nodes. A resource allocation node is disposed adjacent to a portion of the material flow path and one of said activity nodes. The resource allocation node represents a resource utilized in performing a work activity, represented by the adjacent activity node, upon a material represented by the portion of the material flow path.
    Type: Grant
    Filed: May 2, 2006
    Date of Patent: November 11, 2014
    Assignee: Microsoft Corporation
    Inventors: Arthur R. Greef, Jens Olesen Lund, Christian Hagel-Sorensen
  • Patent number: 8874489
    Abstract: Disclosed are a method, a device and a system of short-term residential spaces in a geo-spatial environment. In one embodiment, a method of a short-term listing server comprises validating that a place-to-stay listing data is associated with a verified user of the short-term listing server using a processor and a memory, verifying that a set of geospatial coordinates associated with the place-to-stay listing data are trusted based on a claimed geospatial location of the verified user of the short-term listing server, determining that a time stamp associated with a creation date and a creation time of the place-to-stay listing data is trusted based the claimed geospatial location of the verified user of the short-term listing server, and processing a payment associated with a renter of a space in a private residential home associated with the place-to-stay listing data through the short-term listing server.
    Type: Grant
    Filed: December 10, 2013
    Date of Patent: October 28, 2014
    Assignee: Fatdoor, Inc.
    Inventor: Raj V. Abhyanker
  • Patent number: 8862491
    Abstract: A method and computer program product for integrating risk management concepts into a standard business process metamodel by defining a set of metamodel extensions to standard process modeling languages that incorporate risk information directly in the process model. The method includes collecting risk-relevant information for addition to a business process model, and enabling visualizing of a risk-extended business process model. using a notation to express notions as failure modes of resources, root cause events, and sources of execution failure and low job output quality directly in the context of process models. Additionally, the method enables the computation of risk-related impacts on the distribution of process performance measures using a Bayesian network model or a discrete-event simulation model.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Eric W. Cope, Lea A. Deleris, Dominik Etzweiler, Jana Koehler, Jochen M. Kuester, Bonnie K. Ray
  • Patent number: 8838466
    Abstract: An invention for tracking the status, physical location, and logical location of a workflow object as an object of a particular process is created and progresses logically through the phases of associated with the lifecycle. The workflow object remains, at all times, physically stored in an object repository. Each workflow object has at least one embedded new technology file system (NTFS) tag, wherein the NTFS tag is extended as the workflow object progresses through the phases of a workflow cycle. The embedded and extended NTFS tags define a state of the object progressing through said phases of said workflow cycle. Such embedded and extended NTFS tags can be extracted to obtain properties, methods, and events associated with a requested object, and a GUI displays the extracted information indicating status, physical location, and logical location of one or more workflow objects in a workflow cycle.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: September 16, 2014
    Assignee: Guard Insurance Group
    Inventors: John H. Richardson, Carl J. Witkowski
  • Patent number: 8812339
    Abstract: Non-pending tasks having no pending due dates (e.g., past due tasks) are scheduled with pending tasks having pending due dates by first generating a hypothetical schedule and then an actual schedule. The hypothetical schedule is generated by distributing hours to complete pending tasks as evenly as possible over as many days as possible up to respective due dates; then scheduling non-pending tasks during hours normally available for work and which are not distributed to pending tasks; and then recording as quasi due dates for respective non-pending tasks the dates that the respective non-pending tasks would be completed on the hypothetical schedule. The actual schedule is then generated by scheduling non-pending tasks with pending tasks in chronological order, according to pending due dates for pending tasks, and quasi due dates for non-pending tasks.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: August 19, 2014
    Inventor: Jack D. Stone, Jr.
  • Patent number: 8799051
    Abstract: Computer systems and methods are disclosed for improving professional services delivery, such as services in a data management environment. In certain examples, computer systems comprise portals for transmitting and receiving information from parties involved in the performance and receipt of professional services. For instance, a first portal can receive data (e.g., from sales personnel) descriptive of a customer's product environment. A manager module populates a record with the data, and a second portal provides the customer with access to the record for review, correction and/or validation prior to the generation of a Statement of Work or other like project description. The second portal can also request additional information from the customer regarding the product environment. The manager module compares the data received through the first portal with the customer-entered information to identify and/or address discrepancies between the sets of data and customize the generation of the Statement of Work.
    Type: Grant
    Filed: April 1, 2013
    Date of Patent: August 5, 2014
    Assignee: CommVault Systems, Inc.
    Inventors: Robert Keith Brower, Jr., Peter Messore
  • Patent number: 8799177
    Abstract: Embodiments of the present invention provide a method, a computer-readable storage medium, and an apparatus for building a small business social graph. During operation, the system receives a collection of data from a first business. Next, the system determines if a first node for the first business exists in a social graph, wherein the social graph is a graph-based data model that indicates relationships among various businesses. If not, the system adds the first node for the first business to the social graph. The system then analyzes the collection of data to identify a second business. Next, the system determines if a second node for the second business exists in the social graph. If not, the system adds the second node for the second business to the social graph. Finally, the system adds a relationship between the first node and the second node to the social graph to indicate the relationship between the first business and the second business.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: August 5, 2014
    Assignee: Intuit Inc.
    Inventors: Sundar Saiprasad, Seegler Ittyavirath