Abstract: A lead frame has a die pad with an array of surrounding leads connected at their sides by tie bars and at their ends by coupling bars which are connected through narrow supports to surrounding side rails or partition frames. Positioning holes are provided as positioning references in the coupling bars when the coupling parts of the leads such as the tie bars are removed to separate the leads from the lead frame.

Abstract: Uniaxially conductive connector formed in situ on microchip by laser drilling an insulating layer at least 5 micrometers thick to provide holes communicating with the chip bonding sites, and depositing metal in the holes to establish electrical connection with the bonding sites. Excimer U.V. laser ablation of a polyimide insulating layer is preferred, followed by removal of a surface layer (preferably of amorphous polyamide from the insulating layer to expose the ends of the metal deposited in the holes.

Abstract: An antifuse may be fabricated as a part of an integrated circuit in a layer located above and insulated from the semiconductor substrate. The antifuse includes a lower first electrode, a first dielectric layer disposed over the lower first electrode, a layer of amorphous silicon disposed above the first dielectric layer, a second dielectric layer disposed above the amorphous silicon layer, and an upper second electrode disposed above the second dielectric layer.

Abstract: Self-aligned HFETS are fabricated by providing a semi-insulating substrate and forming a low bandgap III-V semiconductor layer thereon. A first dielectric layer of a first dielectric material is formed on the III-V layer and first and second openings are formed through the first dielectric layer and the III-V layer. After forming dielectric spacers of a second dielectric material on the sidewalls of the first and second openings, gates are formed therein. The first dielectric layer is subsequently removed and source and drain regions are formed in the III-V layer and substrate adjacent to each of the gates. The formation of the source and drain regions is self-aligned to the gates. After forming isolation regions between devices, ohmic contacts to the source and drain regions, all being of a like material, are formed. This formation is also self-aligned to the gates.

Abstract: The method of producing a semiconductor device includes the steps of forming a groove having a predetermined pattern shape on the surface of a substrate; forming a metal film on the substrate while reaction with the surface of the substrate is suppressed; and agglomerating the metal film by in-situ annealing, wherein agglomeration of the metal film is started before the metal film reacts with the surface of the substrate due to annealing, while formation of a native oxide on the metal film is suppressed, and whereby the metal film is filled into the groove by annealing at a predetermined temperature for a predetermined period of time. The structure of the semiconductor device includes an insulator in which there is formed a groove portion having a predetermined pattern shape and an electrode interconnection made of a single-crystal metal which is filled in the groove portion.

Abstract: According to this invention, there is provided a method of manufacturing a compound semiconductor which can be formed at a high yield and in which variations in characteristics of elements caused by variations in distances between a source and a gate and between a drain and the gate can be minimized. In addition, there is provided a compound semiconductor device having a structure capable of increasing a power gain and obtaining a high-speed operation. According to this invention, an active layer is formed on a compound semi-conductor substrate, and source/drain electrodes are formed on the active layer to be separated from each other. The wall insulating films are respectively formed on side walls of the electrodes, and a gate electrode is formed between the side wall insulating films to be respectively in contact therewith.

Abstract: This invention relates to a substrate for mounting a semiconductor chip in an integrated circuit wherein a sintered compact containing copper at 2 to 30 wt. % and tungsten and/or molybdenum is employed as a substrate which efficiently radiates heat developed from the semiconductor chip mounted thereon and said substrate having a thermal expansion coefficient similar to those of semiconductor chip and other enclosure materials.

Abstract: After partially crystallizing an amorphous semiconductor deposited on a substrate, the irradition of infrared ray is conducted to grow a polycrystalline semiconductor layer on the crystallized region and the amorphous region by thermal decomposition while the temperature of the crystallized region is kept higher than that of the amorphous region. Since the polycystalline layer is formed of polycystalline grains grown from nuclei of the cystallized region, the crystal grain thereof is large.

Abstract: The punchthrough capacity of a p-type semiconductor device is significantly improved by nonuniformly doping the p-channel with n-type implants such as phosphorus. The n-type dopants are implanted at large angles to form pocket implants within the channel region. The dose of the implants, angle of the implants and the thermal cycle annealing of the implants will be optimized for maximum punchthrough capability without substantially detracting from the performance of the semiconductor device.

Abstract: A method for fabricating semiconductors is provided in which a conformal layer is formed superjacent at least two conductive layers. The conformal layer has a thickness of at least 50 .ANG.. A barrier layer is then formed superjacent the conformal layer to prevent subsequent layers from diffusing into active regions. The barrier layer is preferably Si.sub.3 N.sub.4. A glass layer is then formed superjacent the barrier layer. The glass layer has a thickness of at least 1 k.ANG.. The glass layer is heated to a temperature of at least 800.degree. C. for at least 15 minutes while introducing H.sub.2 and O.sub.2 at a high temperature to cause vaporization, thereby causing the glass layer to reflow. Next, the glass layer is exposed to a gas and radiant energy for 5 to 60 seconds, thereby making said glass layer planar. The radiant energy generates a temperature within the range of 700.degree. C. to 1250.degree. C. Further, the gas is at least one of N.sub.2, NH.sub.3, O.sub.2, N.sub.2 O, Ar, Ar-H.sub.2, H.sub.

Abstract: An apparatus and method for controlling unwanted spread of adhesive used to attach a semiconductor integrated circuit die to an integrated circuit package assembly. A barrier prevents the adhesive from spreading onto bond finger connections of the integrated circuit package. The barrier may be a solder mask ring outside of and encircling the perimeter of the die attachment area of the package assembly. The barrier is located between the die attachment area and the adjacent bond fingers of the package.

Abstract: A method of forming a via plug in a semiconductor device is disclosed. Metal nuclei are formed on the surface of the metal layer underlying the via hole. The metal layer, which is partially exposed between metal nuclei, is etched by means of a wet etching method, and accordingly, a plurality of etching grooves is formed on the partially exposed surface of the metal layer. As a result, the formation of such grooves has the effect of increasing the bottom surface area of the via hall, thereby increasing the adhesive strength to a contact surface of the via hall and decreasing the via resistance.

Abstract: A semiconductor device or an integrated circuit includes a heterojunction bipolar transistor. The transistor includes an emitter region, a base region, and a transistor electrode. The emitter region is made of first material having a first forbidden band gap. The base region is made of second material having a second forbidden band gap. The first forbidden band gap is wider than the second forbidden band gap. The transistor electrode is made of third material. A capacitor includes a plurality of capacitor electrodes which contain a capacitor electrode made of the third material. The transistor and the capacitor are electrically connected.

Abstract: Method for manufacturing lateral bipolar transistors on a SOI substrate, whereby a basic doping for the conductivity type of emitter and collector is produced in the silicon layer of this SOI substrate, insulation regions are produced outside the region provided for the transistor, contact layers and dielectric layers are applied over a highly doped emitter zone and over a highly doped collector zone produced by a mask technique and are structured, so that a trench is located over a base zone to be produced and in the middle between emitter zone and collector zone, an auxiliary layer is then conformally deposited surface-wide with constant thickness, as a result whereof the trench having the width is reduced to a gap having the width of the base zone to be produced, an implantation of dopant for the operational sign of the conductivity of the base is undertaken through this gap, the regions situated laterally relative to this base zone are shielded by the vertical portions of the auxiliary layer that cover th

Abstract: A first sheet of photomask is used when a gate electrode and a gate bus line are formed, a second sheet of photomask is used when patterning is applied to a semiconductor film which becomes an active layer of a transistor on the gate electrode, a third sheet of photomask is used when a pixel electrode, a source electrode, a drain electrode, a drain bus line and a drain bus terminal portion are formed, and a fourth sheet of photomask is used when a film on the drain bus terminal portion, the gate bus terminal portion and pixel portion is removed, thereby to form thin film transistors arranged in a matrix form.

Abstract: A method for fabricating a semiconductor device including carrying out an ion implantation into a predetermined region of a single-crystal silicon substrate to form therein an amorphized ion-implanted layer according to any one of the methods: (A) implanting an ion of an atom serving as carrier into the predetermined region, followed by implanting an ion of an electrically inert atom or molecule into the region, (B) implanting an ion of an electrically inert atom or molecule in the region, followed by implanting an ion of an atom serving as carrier in the region, and (C) implanting an ion of a molecule in which an atom serving as carrier is bonded to an electrically inert atom; annealing the substrate in an inert atmosphere to crystallize the amorphized ion-implanted layer again; and further annealing the substrate in an oxidizing atmosphere to eliminate defects at the interface of the substrate and the ion implantation layer.

Abstract: The invention relates to a device for treating micro-circuit wafers, comprising a feed station for cassettes with wafers, at least one treatment station in which wafer carriers and treatment means co-acting therewith are disposed and a transfer station provided with transferring means for removing wafers from the cassettes and placing them in the wafer carriers and, after treatment, removing the wafers from the wafer carriers and re-placing them in the cassettes. At least the feed station and the treatment station are embodied as separate connectable units having in cross section an at least partially regular polygonal periphery, wherein these units connect onto other units at the position of the sides of the regular polygonal periphery.

Abstract: Disclosed is a process for producing a solid, surface bonding between two wafer plates, of which at least one is composed of a semiconducting material, such as e.g. silicon. The process has the following steps: on the cleaned surface of at least one wafer plate a film having a residual moisture from solvents containing silicates or phosphates is applied, the two wafer surfaces on at least one of which a film is applied are joined, the two wafers are tempered in the joined state at temperatures lower than approx. 420.degree. C.

Abstract: This is a device and method of forming air gaps in between metal leads comprising. The method comprising: forming the metal leads 51-53 on an insulating layer 50; depositing a nonwetting material layer 56 on the metal leads 51-53 and the insulating layer 50; anisotropically etching the nonwetting material 56 to remove the nonwetting material 56 from open areas and leaving the nonwetting material on side walls of the metal leads 51-53; and depositing a dielectric layer 60 on top of the metal leads 51-53, and the insulating layer 50, whereby the air gaps 58 are produced in between the metal leads 51-53 below the dielectric layer 60. The method may include anisotropically etching at an angle, not vertical, whereby the etching allows removal of the nonwetting material from exterior side walls of the metal leads. The method may also include leaving the nonwetting material layer in between the metal leads. The deposition of the dielectric layer may utilize plasma deposition and spin on techniques.

Abstract: To improve electromigration resistance and stress migration resistance, when a film is formed by depositing Al or Al alloy on a semiconductor substrate, the film is formed stepwise by stepwise changing the heating temperature of the semiconductor substrate at at least two stages.