Abstract: After forming a silicon oxide layer and an amorphous silicon layer on a GaAs substrate in stacking manner, a gate electrode forming opening portion is formed by RIE etching. Then, by selectively removing only the amorphous silicon layer at the portion contacting with the opening portion at the side of the source electrode, a WSi.cndot.TiN.cndot.Pt layer is formed within the opening portion. Subsequently, after applying an organic photoresist layer, an entire surface is etched back to remove at least the WSi.cndot.TiN.cndot.Pt layer above the amorphous silicon layer. Then, by using the WSi.cndot.TiN.cndot.Pt layer remaining in the opening portion as a plating electrode, an Au layer is plated to form a reversed L-shaped gate electrode with an overhanging portion only extending toward the source electrode.

Abstract: A silicon dioxide film and a silicon nitride film are sequentially deposited on an n-type silicon substrate in this order. After the silicon nitride film is selectively removed to form openings, an impurity (boron) for forming a channel stopper is diagonally implanted through the resultant openings. In this case, the direction of the ion implantation, which is projected in a plane perpendicular to the direction of the channel length of a FET in a memory cell region, is 45.degree. tilted with respect to the direction of the normal of the surface substrate, so that implanted boron reaches the end portion of the channel region. Thereafter, LOCOS films are formed and, simultaneously, an impurity (boron) for threshold adjustment is implanted into the respective FET formation regions of the memory cell region and of a peripheral circuit region.

Abstract: A method of fabricating a vertical bipolar semiconductor device includes a step of forming an N.sup.- -type silicon epitaxial layer which constitutes a part of a collector region and a P.sup.+ -type polycrystalline silicon film which functions as a base lead-out electrode. The silicon epitaxial layer and the polycrystalline silicon film are insulated by a silicon oxide film which is a sufficiently thick insulating film, covers the silicon epitaxial layer and has an opening. In this opening, by selective growth of a first and a second semiconductor film and ion implantation using a first insulating film spacer, there are formed a P.sup.- -type single crystal silicon layer, a P.sup.+ -type polycrystalline silicon film, a P.sup.+ type single crystal silicon layer (intrinsic base region), a P.sup.+ -type polycrystalline silicon film, and an N-type single crystal silicon layer.

Abstract: This invention encompasses using a strengthened shell to enhance reliability of aluminum leads of a semiconductor device. The invention includes depositing an aluminum layer on a substrate 12, etching the aluminum layer in a predetermined pattern to form aluminum leads 16, exposing the aluminum leads 16 to a strengthening gas to react and form a strengthened shell 18 on the aluminum leads 16, and depositing a dielectric layer 20 over the strengthened shell 18 and the substrate 12. The strengthening gas may contain nitrogen, oxygen, or both. The exposing step may also comprise a rapid thermal anneal, and the dielectric layer 20 is preferably comprised of a material having a dielectric constant of less than 3. An advantage of the invention is to mechanically strengthen the aluminum leads of a semiconductor wafer. In addition, it is an intrinsic operation, rather than extrinsic; the basic material required is already present on the wafer, it is merely altered.

Abstract: A method for fabricating a thin film transistor which includes steps for, forming a first and a second gate electrode on a transparent insulation substrate, forming a gate insulation film on the exposed surface and forming an active layer on a surface of the gate insulation film overlying the first gate electrode, forming a transparent conductive material pattern on a surface of the active layer overlying the first gate electrode and a pixel electrode on the surface of the gate insulation film extending laterally from the surface of the second gate electrode toward the active layer, forming a source electrode over the surfaces of the active layer and a drain electrode which extends from the other side of the transparent conductive material across the active layer to the surface of one side of the pixel leaving space between the source electrode and the drain electrode, an ohmic contact semiconductor layer automatically formed beneath the source electrode and the drain electrode, removing the exposed semicondu

Abstract: A process for fabricating an IGFET integrated circuit having two gate dielectric layers with different parameters is provided. Typically, the process is used for fabrication of dual voltage CMOS integrated circuits. The integrated circuit may include high voltage transistors having a first gate dielectric thickness and low voltage transistors having a second gate dielectric thickness. A first gate dielectric layer and a first gate layer for the high voltage transistors are formed over active regions of a substrate. The device is patterned to expose low voltage transistor areas, and the first gate dielectric layer and the first gate layer are removed in the low voltage transistor areas. Then, a second gate dielectric layer and a second gate layer for the low voltage transistors are formed on the device. The device is patterned to expose the high voltage transistor areas, and the second gate dielectric layer and the second gate layer are removed in the high voltage transistor areas.

Abstract: Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.

Abstract: An insulating film and a silicon nitride film are formed on a semiconductor substrate. A resist film is patterned on the silicon nitride film. Thereafter, using the patterned resist film as a mask, the silicon nitride film is removed in such a manner that the film thickness is the maximum at its center portion and becomes gradually small downwardly in the neighborhood of the ends of the resist film pattern. The silicon nitride film which is thick at its center portion is adopted as a mask for selective oxidation.

Abstract: A structure and method for fabricating a field effect transistor (FET) having improved drain to source punchthrough properties was achieved. The method utilizes the selective deposition of silicon oxide by a Liquid Phase Deposition (LPD) method to form a self-aligning implant mask. The mask is then used to implant a buried anti-punchthrough implant channel under and aligned to the gate electrode of the FET. The buried implant reduces the depletion width at the substrate to source and drain junction under the gate electrode but does not increase substantially the junction capacitance under the source and drain contacts, thereby improving punch-through characteristic while maintaining device performance.

Abstract: This invention relates to an improved solid state suppressor and a method for making the same. Due to the fact that at least part of the substrate is substituted during fabrication of the suppressor, it is possible to produce a suppressor having a substrate which has an effective thickness that is less than the physical thickness of the slice. This allows for a good functioning suppressor which is unlikely to break during fabrication.

Abstract: A method for manufacturing a TFT of a SRAM in a highly-integrated semiconductor device, to enlarge the grain size of a polysilicon film, includes steps of depositing amorphous silicon film under a pressure capable of maintaining a uniform thickness thereof, and forming a polysilicon film which has a maximized grain size in the same tube that the amorphous silicon film has been deposited, while performing an annealing process by raising the temperature to 600.degree.-650.degree. C. for 4-10 hours under the pressure which is lowered to approximately 10.sup.-3 Torr. The polysilicon film having a maximized grain size is utilized as the channels of the TFT.

Abstract: This is a fabrication process for complementary III-V HFETs in which devices are built side-by-side in doped-areas, known as "tubs", grown by molecular beam epitaxy on indium phosphide (InP) substrates, or other material systems such as materials grown on GaAs substrates. The layers grown are a semi-insulating buffer layer of InAlAs, a InGaAs channel, an InAlAs barrier layer and finally an InGaAs cap layer. All layers are lattice matched or pseudomorphic to the InP substrate. After mesa etching of areas around the transistor, a high temperature silicon nitride (Si.sub.3 N.sub.4) layer is deposited using chemical vapor deposition, and photoresist is deposited. Then n-well and p-well areas are formed in turn, with appropriate ion-implantation, stripping of the photoresist, and annealing to activate the dopants. Then the Si.sub.3 N.sub.4 is stripped and the samples thoroughly cleaned. Then, the refractory gate metal is sputtered, delineated with photoresist and reactive ion etch procedures.

Abstract: A process of forming complementary insulated gate field effect transistors includes forming first and second well regions of first and second conductivity types in a planar semiconductor layer so that the well regions have an impurity retrograde impurity distribution profile. An insulator layer is then selectively formed with a first relatively thick insulator portion and thin gate portions. The first and second gates are formed on the relatively thin portions of the insulator layer. Insulator spacers are formed so as to extend laterally from the gates and from the relatively thick insulator portion. First impurities are introduced using the first gate and spacers as a mask to form first source and drain regions. Second impurities of an opposite conductivity type are introduced using the second gate and spacers as a mask to form source and drain regions of a complementary device.

Abstract: In a method of manufacturing a semiconductor device, a metal film including a metal element is formed on a wiring base layer by ion beam assisted CVD, more specifically, by selectively irradiating a region of the wiring base layer with a focused ion beam while blowing an organic metal gas containing the metal element onto the region irradiated by the ion beam. Thereafter, a low-resistance metal layer is formed on the metal film by electroless plating. Therefore, a metal wiring of low resistivity with a predetermined pattern is formed without a photolithographic process using a resist and also without sputtering or selective etching of the metal film. Consequently, manufacturing costs of a semiconductor device are significantly reduced.

Abstract: The present invention relates to an electrode forming process for forming an ohmic contact on a compound semiconductor crystal of a GaAs-based material having p-type conductivity. The process includes a first step of depositing a thin Pt layer having a thickness larger than 50 .ANG. on the compound semiconductor crystal, and a second step of depositing a Ti/Pt/Au electrode on the Pt layer.

Abstract: An electronically erasable and reprogrammable memory integrated circuit device having split-gate memory cell with separated tunneling regions and its process of fabrication are disclosed. A silicon substrate having field oxide layers isolating component regions are processed to construct a memory cell in each of the isolated component region. Each of the memory cells includes a drain and source region formed in the silicon substrate, with a channel formed between the drain and source regions. Ring-shaped floating gate surrounds and covers the periphery of the channel and is isolated with the drain and source regions respectively by two thin tunneling oxide layers that are separated from each other. The two separated tunneling oxide layers constitute two separated tunneling regions. A control gate layer covers the ring-shaped floating gate and the portion of the channel that is not covered by the floating gate layer, and is separated from the floating gate by an isolation layer.

Abstract: Insulated gate field effect transistors (10, 70) having independent process steps for setting lateral and vertical dopant profiles for source and drain regions. In a unilateral transistor (10) , portions (48, 50, 51, 55) of the source region are contained within a halo region (34, 41) whereas portions (49, 47, 52, 64) of the drain region are non contained within a halo region. The source region (60, 65) has a first portion (48, 51) for setting a channel length and a second portion (50, 55 ) for setting a breakdown voltage and a source/drain capacitance. The second portion (50, 55) extends further into the halo region than the first portion (48, 51). In a bilateral transistor (70), portions (84, 89, 90, 91) of the drain region (72, 87) are contained within halo region (75, 79 ).

Abstract: An MOS device is provided having a drain- or source-side implant into the channel region in order to minimize short-channel effects. Implant into the channel region is achieved using conventional processing techniques, wherein the channel implant is directed substantially perpendicular to the upper surface of the substrate. Numerous masking steps and reorientation of the substrate is not needed. Additionally, the drain- or source-side implant mask can be formed from currently existing masks and incorporated into a standard processing flow for either a standard MOS device or a memory array comprising dual-level polysilicon. If drain-side implant is chosen, then the lateral demarcation line between the drain implant and the substrate is preferably placed within the channel region, and preferably near a mid-point within the channel a spaced distance below a subsequently placed, overlying polysilicon.

Abstract: This invention relates to a method for fabrication of MOS transistors having LDD(Lightly Doped Drain) structure which comprises the steps of forming a gate insulation film on a semiconductor substrate of a first conduction type, forming a conduction layer for forming a gate pole on the gate insulation film, forming an oxidation prevention layer on the conduction layer, carrying out selective etchings of the oxidation prevention layer and the conduction layer to a certain thicknesses of areas except the gate pole area, forming an oxide film by an oxidation of the exposed portion of the conduction layer, carrying out a selective etching of the oxide film by using the oxidation prevention layer as a mask, forming a high density impurity area of a second conduction type in a predetermined area of the semiconductor substrate by a high density ion injection of the second conduction type impurity, removing the oxidation prevention layer and the oxide film, forming a low density impurity area of the second conduction

Abstract: A heterojunction device including a first semiconductive layer on a substrate, a barrier layer on the first layer, a second semiconductive layer on the barrier layer and a multi-layer cap, on the second semiconductive layer. First and second gates positioned on layers of the cap to define first and second transistors, with the cap layers being selected and etched to pin the Fermi level in a first transistor conduction channel in the second semiconductive layer such that the number of carriers in the first conduction channel are substantially less than the number of carriers in surrounding portions of the second semiconductive layer and the Fermi level in a second transistor conduction channel in the first semiconductive layer such that the number of carriers in the second conduction channel are substantially less than the number of carriers in surrounding portions of the first semiconductive layer.