Abstract: In a SCSI subsystem having mixed wide and narrow SCSI devices installed, a method and apparatus is provided for detecting a narrow SCSI device illegally installed at a slot assigned to a wide SCSI device. To detect the narrow SCSI device installed at an illegal location, high ID and low ID SCSI bus address pairs are set as test pairs for the SCSI subsystem. The low ID is the alias of the high ID if a narrow SCSI device is installed at the high ID slot. To detect a conflict with a controller ID, a non-responsive ID bus address corresponding to a slot known to be unused is called. A response to this call indicates a narrow SCSI device is installed at the high ID of the test pair and the narrow SCSI device at the high ID has configured to an alias bus address matching the controller ID. To detect a present conflict between SCSI devices, the low ID bus address in the test pair is called.

Abstract: The present invention provides a personal computer system for receiving and retaining data and capable of securing data retained within the system against unauthorized access. More particularly, the system includes a computer including a processor and a detachable input/output (I/O) device that functions as a conventional computer interface when docked to the computer and wherein the computer system enters a suspend mode when the detachable I/O device is detached from the computer whereby the system data is secured against unauthorized access. A security module controls access to at least certain levels of data retained within the system by distinguishing between the detachable I/O device docked to the computer and the detachable I/O device detached from the computer. A docking station is coupled to the processor and is detachably coupled to the detachable I/O device.

Abstract: Computing modules can cooperate to tolerate faults among their members. In a preferred embodiment, computing modules couple with dual-ported memories and interface with a dynamically reconfigurable Field-Programmable Gate Array ("FPGA"). The FPGA serves as a computational engine to provide direct hardware support for flexible fault tolerance between unconstrained combinations of the computing modules. In addition to supporting traditional fault tolerance functions that require bit-for-bit exactness, the FPGA engine is programmed to tolerate faults that cannot be detected through direct comparison of module outputs. Combating these faults requires more complex algorithmic or heuristic approaches that check whether outputs meet user-defined reasonableness criteria. For example, forming a majority from outputs that are not identical but may nonetheless be correct requires taking an inexact vote.