Patents Examined by Brian Hearn
  • Patent number: 5510294
    Abstract: A method is provided for forming a via for multilevel metallization of an integrated circuit, and an integrated circuit formed according to the same. A first conductive layer is formed over the integrated circuit. A first dielectric layer is then, formed over the first conductive layer. A second dielectric layer over the first dielectric layer and a second conductive layer is formed over the second dielectric layer. A photoresist layer is formed and patterned over the second conductive layer to expose a portion of the second conductive layer. The second conductive layer is etched to form an opening exposing a portion of the second dielectric layer. The second dielectric layer is then etched in the opening to form partially sloped sidewalls sloping outward at an upper surface of the dielectric layer. The photoresist layer is removed. The remaining second dielectric layer and the first electric layer is then anisotropically etched in the opening exposing the portion of the first conductive layer in the opening.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: April 23, 1996
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Girish A. Dixit, Fusen E. Chen, Alexander Kalnitsky
  • Patent number: 5508228
    Abstract: Compliant electrically connection bumps for an adhesive flip chip integrated circuit device and various methods for forming the bumps include the steps of forming polymer bumps on a substrate or an integrated circuit die and coating the polymer bumps with a metallization layer. The polymer bump forming step includes the steps of coating a polymer material on a substrate, curing the polymer and the etching the bump pattern from the polymer material. The overcoating step includes electrolessly plating a ductile metal such as gold on the polymer bump.
    Type: Grant
    Filed: February 14, 1994
    Date of Patent: April 16, 1996
    Assignee: Microelectronics and Computer Technology Corporation
    Inventors: Ernest R. Nolan, Diana C. Duane, Todd H. Herder, Thomas A. Bishop, Kimcuc T. Tran, Robert W. Froehlich, Randy L. German, Richard D. Nelson, Chung J. Lee, Mark R. Breen, Kathryn V. Keswick
  • Patent number: 5478766
    Abstract: A process for formation of a thin film transistor liquid crystal display is disclosed, in which an etch-back type 3-mask process or an etch stopper type 4-mask process is applied, so that the semiconductor layer of the thin film transistor can be isolated from the data line. Consequently, the optical leakage current which aggravates the performance of the transistor is inhibited. Further, the data line is composed of a material which has a low chemical reactivity with ITO, so that a corrosion due to a chemical reaction between the data line and ITO can be eliminated.
    Type: Grant
    Filed: March 3, 1995
    Date of Patent: December 26, 1995
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woonyoung Park, Seoklyul Lee
  • Patent number: 5462894
    Abstract: A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.
    Type: Grant
    Filed: September 22, 1994
    Date of Patent: October 31, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Charles R. Spinner, Fu-Tai Liou
  • Patent number: 5459104
    Abstract: The invention relates to a process of production of a semiconductor substrate by binding etc. involving the direct polishing of an oxide film with step differences. A silicon oxide film (3) having step differences is formed on at least one surface of an active layer substrate (A). This silicon oxide film (3) is polished by a rigid platen using a polishing agent comprised primarily of cerium oxide. A support substrate (B) is laminated to the bonding face (3a) this obtained to obtain a wafer of a SOI structure. This enables elimination of the polycrystalline silicon layer on the silicon oxide film which had been formed only for bonding purposes.
    Type: Grant
    Filed: September 19, 1994
    Date of Patent: October 17, 1995
    Assignee: Mitsubishi Materials Silicon Corporation
    Inventor: Shinsuke Sakai
  • Patent number: 5434103
    Abstract: An electrical interconnection method includes: a) providing two conductive layers separated by an insulating material on a semiconductor wafer; b) etching the conductive layers and insulating material to define and outwardly expose a sidewall of each conductive layer; c) depositing an electrically conductive material over the etched conductive layers and their respective sidewalls; and d) anisotropically etching the conductive material to define an electrically conductive sidewall link electrically interconnecting the two conductive layers. Such is utilizable to make thin film transistors and other circuitry.
    Type: Grant
    Filed: April 28, 1994
    Date of Patent: July 18, 1995
    Assignee: Micron Technology, Inc.
    Inventors: Charles H. Dennison, Monte Manning
  • Patent number: 5420062
    Abstract: This invention relates to an insulated gate FET in which the withstanding voltage and the latch-up resistant property are both made high. The structure thereof includes a second well formed in a first well and having an impurity concentration lower than that of the first well. Source and drain electrodes of the FET are formed in the second well.
    Type: Grant
    Filed: April 20, 1994
    Date of Patent: May 30, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nakfumi Inada, Osamu Takata
  • Patent number: 5416030
    Abstract: A method is provided for reducing leakage current in an integrated circuit (24). A first doped region (18) having a first conductivity type is formed in a semiconductor layer (10) having a second conductivity type, such that a second doped region (20) having the first conductivity type is formed in the semiconductor layer (10). The second doped region (20) is less conductive than the first doped region (18). The first doped region (18) is removed from the semiconductor layer (10), such that the second doped region (20) substantially remains in the semiconductor layer (10). The integrated circuit (24) is formed to include the second doped region (20) and the semiconductor layer (10).
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: May 16, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Jerome L. Elkind, Lissa K. Magel
  • Patent number: 5413951
    Abstract: A method for fabricating an SOI structure which includes the steps of contacting a single crystal layer of a group III-V compound semiconductor material to a single crystal substrate of sapphire such that a principal surface of said single crystal layer establishes an intimate contact with a corresponding principal surface of said single crystal substrate and bonding the single crystal layer and the single crystal substrate with each other while elevating a temperature.
    Type: Grant
    Filed: February 19, 1993
    Date of Patent: May 9, 1995
    Assignee: Fujitsu Limited
    Inventors: Tatsuya Ohori, Isamu Hanyu, Fumitoshi Sugimoto, Yoshihiro Arimoto
  • Patent number: 5407842
    Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: April 18, 1995
    Assignee: Texas Intruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5376563
    Abstract: Using a silicon etched technique to remove an implanted base and emitter surrounding emitter-base islands, a "mesa" emitter structure can be formed. Using the structure, a self aligned P+ can be formed around emitter-base islands.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: December 27, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: William P. Imhauser
  • Patent number: 5376591
    Abstract: A, method for forming semiconductor device, includes forming an insulating film on a body by chemical vapor deposition, at low temperature raising the temperature of, the body, and exposing the body to plasma gas.
    Type: Grant
    Filed: June 8, 1992
    Date of Patent: December 27, 1994
    Assignee: Semiconductor Process Laboratory Co., Ltd.
    Inventors: Kazuo Maeda, Noboru Tokumasu, Yuko Nishimoto
  • Patent number: 5376561
    Abstract: The invention relates to device processing, packaging and interconnects that will yield integrated electronic circuitry of higher density and complexity than can be obtained by using conventional multi-chip modules. Processes include the formation of complex multi-function circuitry on common module substrates using circuit tiles of silicon thin-films which are transferred, interconnected and packaged. Circuit modules using integrated transfer/interconnect processes compatible with extremely high density and complexity provide large-area active-matrix displays with on-board drivers and logic in a complete glass-based modules. Other applications are contemplated, such as, displays, microprocessor and memory devices, and communication circuits with optical input and output.
    Type: Grant
    Filed: April 24, 1992
    Date of Patent: December 27, 1994
    Assignee: Kopin Corporation
    Inventors: Duv-Pach Vu, Brenda Dingle, Ngwe Cheong
  • Patent number: 5374566
    Abstract: A method of fabricating a bipolar transistor on a semiconductor wafer is provided. The method includes steps of implanting p-type dopants into diffusion compensation regions (23) where an intrinsic base region (18) intersects an isolation oxide (31). The implant step is carried out before depositing a poly layer (from which an emitter contact (27a) is formed). Thus, the diffusion compensation region (23) is also located below the emitter contact (27a). A diffused emitter (27b) is subsequent formed by diffusing dopant from the emitter contact (27a) into the underlying active area.
    Type: Grant
    Filed: January 27, 1993
    Date of Patent: December 20, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Ali Iranmanesh
  • Patent number: 5372951
    Abstract: A field oxide is provided which purposefully takes advantage of fluorine mobility from an implanted impurity species. The field oxide can be enhanced or thickened according to the size (area and thickness) of the oxide. Fluorine from the impurity species provides for dislodgement of oxygen at silicon-oxygen bond sites, leading to oxygen recombination at the field oxide/substrate interface. Thickening of the oxide through recombination occurs after it is initially grown and implanted. Accordingly, initial thermal oxidation can be shortened to enhance throughput. The fluorine-enhanced thickening effect can therefore compensate for the shorter thermal oxidation time. Moreover, the thickened oxide regions are anistropically oxidized underneath existing thermally grown oxides and directly underneath openings between nitrides. The thickened oxides therefore do not cause additional shrinkage of the active areas which reside between field oxides.
    Type: Grant
    Filed: October 1, 1993
    Date of Patent: December 13, 1994
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mohammed Anjum, Ibrahim K. Burki, Craig W. Christian
  • Patent number: 5369056
    Abstract: The present invention provides a method for fabricating modified integrated circuit packages that are ultra-thin and resist warping. The integrated circuit packages are made thinner by removing some of the casing material uniformly from the upper and lower major surfaces of the integrated circuit package. To prevent the resulting ultra-thin integrated circuit package from warping, a thin layer of material with a coefficient of thermal expansion less than that of silicon is mounted to the upper major surface of the package after some of the casing material has been removed uniformly from the upper major surface. Also, a thin layer of material with a coefficient of thermal expansion greater than that of silicon may be mounted to the lower major surface of the package after some of the casing material has been removed uniformly from the lower major surface. The result is an ultra-thin integrated circuit package that is thermally and mechanically balanced to prevent warping.
    Type: Grant
    Filed: March 29, 1993
    Date of Patent: November 29, 1994
    Assignee: Staktek Corporation
    Inventors: Carmen D. Burns, James W. Cady, Jerry M. Roane, Phillip R. Troetschel
  • Patent number: 5366915
    Abstract: In a process of fabricating a floating gate type field effect transistor, an ion implantation for forming a drain region is repeated more than twice at different angles, and the drain region has an impurity profile gently changed by virtue of the ion implantation at the different angles so that a drain disturbe is effectively suppressed, thereby improving the stability of the data bit stored in the floating gate type field effect transistor.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: November 22, 1994
    Assignee: NEC Corporation
    Inventor: Noriaki Kodama
  • Patent number: 5366923
    Abstract: A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.
    Type: Grant
    Filed: December 8, 1993
    Date of Patent: November 22, 1994
    Assignee: International Business Machines Corporation
    Inventors: Klaus D. Beyer, Chang-Ming Hsieh, Louis L. Hsu, Tsorng-Dih Yuan
  • Patent number: 5366933
    Abstract: A method for constructing a dual sided integrated circuit chip package. A leadframe is formed comprising a set of die pads, and a set of lead fingers corresponding to each die pad. An integrated circuit die is disposed onto a first side and a second side of each die pad. Each integrated circuit die is wire bonded to the corresponding lead fingers. The temperature during the second side die attach and wire bonding steps is controlled and/or compatible materials are selected to prevent warping of the leadframe, and special steps are also implemented to eliminate mold flash, plastic mold cracking and overcuring and increasing the adhesion.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: November 22, 1994
    Assignee: Intel Corporation
    Inventors: Suresh V. Golwalkar, Richard Foehringer, Michael Wentling, Ryo Takatsuki, Shigeo Kawashima
  • Patent number: 5366909
    Abstract: A method for fabricating a thin film transistor capable of increasing an ON/OFF current ratio and decreasing a consumption of electric power.
    Type: Grant
    Filed: February 23, 1994
    Date of Patent: November 22, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventors: Seung R. Song, Hong S. Kim