Abstract: A semiconductor device having a protective insulating film is disclosed. This semiconductor device includes a semiconductor substrate, and an interconnection pattern provided on said semiconductor substrate and electrically connected with said elements. A silicon-oxy-nitride film is provided on said semiconductor substrate so as to cover said interconnection pattern. The silicon-oxy-nitride film is deposited in accordance with a chemical vapor deposition Method using plasma, using a mixture gas including organic silane and a nitriding gas and has therefore superior step coverage. The silicon-oxy-nitride film has a superior barrier characteristic to moisture coming in from the outside. A semiconductor device superior in reliability such as moisture resistance is thus obtained.

Abstract: A semiconductor layer undergoes isolation etching and gate recess etching, using a side wall insulating layer having the shape of a forward taper as a mask, by means of the anisotropic etching technique. The shape of the side wall of the semiconductor layer corresponds to that of the forward taper of the mask. The shape of the forward taper is always constant, irrespective of face orientation of crystal of the semiconductor layer. Since the taper angle of the side wall insulating layer can freely be set within a predetermined range in accordance with conditions, the taper angle of the semiconductor layer can be controlled. The design margin of an electrode wiring pattern is greatly improved. Since the side wall of a gate recess is stably formed in the shape of a forward taper, the side wall insulating layer can be formed on the surface of the forward taper and thus a gate electrode layer can be formed so as to have a T-shaped cross section. Therefore, the gate resistance can be greatly reduced.

Abstract: A resistor (45) of semiconductor material is formed on an insulating layer (42), then a silicon nitride film (46) is deposited on the entire surface including the resistor (45), and a silicon dioxide film (47) is sequentially deposited thereon, and thereafter electrodes (49A) and (49B)of the resistor (45) are formed, thereby preventing the fragility of the insulating layer (51) at step portions of the resistor (45), preventing the breakage of the electrodes and interconnections, and improving a withstand voltage between the resistor (45) and the interconnections crossing over it to thereby improve yield of a semiconductor device.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography,. and 3D IC fabrication.

Abstract: A dry etching method whereby an SiO.sub.2 layer and an Si.sub.3 N.sub.4 layer may be etched with high selectivity for each other. As etching gas, such sulfur fluorides as S.sub.2 F.sub.2 are used which, when dissociated by electric discharges, will form SF.sub.x.sup.+ as a main etchant for the SiO.sub.2 layer or F* as a main etchant for the Si.sub.3 N.sub.4 layer and release sulfur in the plasma. When the SiO.sub.2 layer is etched on the Si.sub.3 N.sub.4 layer as an underlying layer via a resist mask, nitrogen atoms, removed from the underlying layer upon exposure thereof to the plasma, will combine with sulfur in the plasma to form on the exposed surface thereof such sulfur nitride compounds as polythiazyl (SN).sub.x, which will, in turn, serve to achieve high selectivity for the underlying layer. The SiO.sub.2 layer can also be etched via an Si.sub.3 N.sub.4 mask patterned into a predetermined shape, in which case sulfur nitride compounds formed on the Si.sub.3 N.sub.

Abstract: A high electron mobility transistor is disclosed, which takes advantage of the increased mobility due to a two dimensional electron gas occurring in GaN/Al.sub.x Ga.sub.1-x N heterojunctions. These structures are deposited on basal plane sapphire using low pressure metalorganic chemical vapor deposition. The electron mobility of the heterojunction is approximately 620 cm.sup.2 per volt second at room temperature as compared to 56 cm.sup.2 per volt second for bulk GaN of the same thickness deposited under identical conditions. The mobility of the bulk sample peaked at 62 cm.sup.2 per volt second at 180.degree. K. and decreased to 19 cm.sup.2 per volt second at 77.degree. K. The mobility for the heterostructure, however, increased to a value of 1,600 cm.sup.2 per volt second at 77.degree. K. and saturated at 4.degree. K.

Abstract: Semiconductor devices having a reduced parasitic capacitance while having a maximum acceptable current similar to those of prior devices, and a method of manufacturing thereof are disclosed. The inventive device has a hole at the bottom of which an insulating film separated from the hole walls is located, a semiconductor film being present in the hole, which is connected to the semiconductor substrate adjacent to the insulating film and a conductor film constituting a portion of the hole wall, and extends onto the insulating film so as to cover at least part of the film.

Abstract: A method for manufacturing a semiconductor device including forming an epitaxial layer on a second conductive silicon substrate selectively provided with a first conductive impurity diffusion layer and diffusing a second impurity through surface of the epitaxial layer to form islands of the epitaxial layer, the above epitaxial layer having a higher specific resistance than that of the silicon substrate.

Abstract: The present method uses a one block out mask method for forming both the N channel and P channel MOS field effect transistors by providing a special oxidizing method that grows sufficient silicon oxide upon the already formed N+ source/drain regions which is sufficient to block the P+ ion implantation which forms the P channel device from the N channel device area.

Abstract: A method for forming integrated circuit structures includes the formation of high-value resistive elements and low resistance interconnect in a single polycrystalline layer. In one embodiment, interconnect regions of the polycrystalline silicon layer are masked, and resistive element regions are partially oxidized to reduce the thickness of the polycrystalline layer in such regions. Resistivity of the interconnect regions may then be reduced by implanting a high level of impurities in them, or by forming a refractory metal silicide layer over the interconnect regions. The oxide formed over the resistive elements during the oxidation thereof protects them from either of the following process steps, so that no masking is required. In an alternative embodiment, silicidation of the interconnect regions of the polycrystalline silicon layer may be performed without the prior local oxidations of the resistive element regions.

Abstract: A memory cell of 1 bit is constituted by 1 selecting transistor and 1 memory transistor in an EEPROM. One of the source-drain regions is commonly used by the selecting transistor and the memory transistor. The commonly used source-drain region is manufactured through the following steps. First, a gate electrode of the transistor is formed. An oxide film is deposited on the entire surface. A resist is applied thereon and is etched back to expose a surface of the oxide film on the gate electrode. Thereafter, the oxide films deposited on the side surfaces of the gate electrode are removed to form opening portions. Impurities are implanted to the silicon substrate utilizing the opening portions.

Abstract: Disclosed is a (4T-2R) SRAM cell and method which achieves a much reduced cell area through the combined use of vertical trench pull-down n-channel transistors and a buried-layer ground plate. The reduced cell area allows the fabrication of a higher density SRAM for a given set of lithographic rules. The cell structure also allows the implementation of a (6T) SRAM cell with non-self-aligned poly-silicon p-channel pull-up transistors without appreciably enlarging the cell area.

Abstract: A silicon integrated circuit includes a vertical power DMOS transistor and a vertical NPN transistor in separate epitaxial pockets by a method including simultaneously forming a plurality of D-well regions in the DMOS transistor and the base region in the NPN transistor, and including simultaneously forming the elemental source regions and the emitter region. N-type buried layers are provided simultaneously in the DMOS and the NPN transistors, respectively. Also formed simultaneously are two N+ plugs connecting the two buried layers, respectively, to the epitaxial surface of the integrated circuit die. None of these economically attractive simultaneous steps requires deviation in either device from optimum geometries. Also disclosed are compatible and integrated steps for forming small signal CMOS transistors. This method also includes a full self-alignment of gate, source and channel regions in the DMOS transistor as well as in the CMOS transistors.

Abstract: The invention relates to a method for the manufacture of insulating portions separating the active regions of a VLSI CMOS circuit wherein an oxide coated silicon substrate is etched in those regions in which minimal insulation is to be required by etching trenches in the oxide insulating layers overlying the minimal insulation regions and generating field oxide regions in the remaining portions separating the active regions. The etching is preferably carried out by a combination of dry and wet etching steps. The field oxide regions may be produced by the well known local oxidation of silicon (LOCOS).

Abstract: This invention relates to a process for purifying a nitrogen trifluoride containing atmosphere contaminated with dinitrogen difluoride. The atmosphere is purified by heating the nitrogen trifluoride atmosphere in the presence of a particulate metal capable of defluorinating dinitrogen difluoride, but inert to nitrogen trifluoride, preferably the metal being selected from the group consisting of iron, cobalt, and nickel, to a temperature of from about 300.degree.-1000.degree. F. for a time sufficient to effect defluorination of the dinitrogen difluoride.

Abstract: Double bond isomerization and disproportionation of olefins is obtained by contact with a catalyst in a single-stage composition containing a support, uranium, and at least one of tungsten, molybdenum, or rhenium.

Abstract: A process for producing chlorine dioxide which comprises(1) feeding hydrochloric acid and an excess on a stoichiometric basis of sodium chlorate produced in an electrolytic cell for producing sodium chlorate into a reaction zone for producing chlorine dioxide;(2) reacting the hydrochloric acid and the sodium chlorate in the reaction zone to form a gaseous reaction product containing chlorine dioxide and chlorine and so that sodium chloride produced is precipitated to form a slurry-like residual reaction mixture containing the precipitated sodium chloride;(3) continuously removing the chlorine dioxide as the gaseous reaction product;(4) simultaneously withdrawing the slurry-like residual reaction mixture containing the precipitated sodium chloride continuously from the reaction zone;(5) feeding water to the withdrawn residual reaction mixture to dissolve the sodium chloride and form a solution containing sodium chloride;(6) blowing air or an inert gas through the solution containing sodium chloride to remove a

Abstract: A process is described for the recovery of copper values from an acidic aqueous solution containing copper values by means of liquid-liquid extraction, wherein the extractant is a mixture comprising a substantially water-immiscible organic solvent, one or more hydroxyoximes capable of extracting copper values, and one or more alpha, betadioximes of the anti-configuration. Novel alpha, beta-dioxime compounds are also disclosed.

Abstract: A method for the preparation of manganous chloride solutions using copper as a redox intermediate in the reaction between manganese and chlorine. Treatment of manganese-containing materials with a copper solution results in oxidation and dissolution of the manganese and the formation of elemental copper. The copper is in turn dissolved by reaction with cupric or ferric ions, which are then regenerated by chlorine oxidation.

Abstract: This invention provides a process for treating a nickel matte to recover essentially pure nickel comprising: treating an aqueous mixture of the matte with chlorine to produce a solid residue and an aqueous lixiviating solution having a pH value which is substantially nil or positive; treating the lixiviating solution to produce a solution containing primarily nickel chloride; and electrolyzing the solution to recover pure nickel at the cathode.