Abstract: The disclosure provides a microcontroller which has an internal timing device for generating an internal clock signal, at least one terminal contact for receiving an external clock signal, a clock changing device and a timer module, which is electrically conductively connected to the at least one terminal contact and to the internal timing device and, after the microcontroller has been switched on, is set up to determine a frequency of the external clock signal by means of the clock signal, and to determine at least one parameter by means of which the clock changing device can be set up to change the external clock signal into a useful clock signal with a predefined frequency.

Abstract: Systems and methods for managing performance in heterogenous computing platforms of IHS (Information Handling Systems) are described. In an illustrative, non-limiting embodiment, a heterogeneous computing platform includes devices and a memory storing firmware instructions. Based on execution of these firmware instructions by a respective device, a corresponding firmware service is provided such that one of the devices operates as an orchestrator. The orchestrator receives reports of changes in context of operation of the IHS by a user and based on the change in user context, determines responsiveness settings that are mapped to the reported user context, where the responsiveness settings adjust thread management policies by one or more processors of the heterogeneous computing platform. The orchestrator configures the one or more processors of the heterogeneous computing platform based on the responsiveness settings, and thus adjusts the performance of the IHS in response to the change in user context.

Abstract: A Power-over-Ethernet (POE) powered device (PD) may be coupled to two power sourcing equipments (PSEs), a PSE and an additional PSE. The PSE may exchange a transport layer protocol communications with the additional PSE. The communications comprising a first communication from the PSE to the additional PSE indicative of a PoE configuration of the PSE and a second communication from the additional PSE to the PSE indicative of a PoE configuration of the additional PSE. The PSE may create a power availability table based on the communications. The PSE may detect occurrence of an event comprising at least one of a change in the power availability table or a change in ability of the PSE to provide power to the PD. On occurrence of the event, the PSE may send additional communications to the additional PSE, requesting to adjust its power allotment for the PD.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: In one embodiment, a power control block includes a power input for receiving pulse power from a power source, a power output coupled to a transmission line connector, a pulse power module operable to receive the pulse power and transmit the pulse power to the power output, a Power over Ethernet (PoE) module operable to receive the pulse power and transmit PoE to the power output, and a power controller for selecting the pulse power module to deliver the pulse power to the power output or the PoE module to deliver the PoE to the power output.

Abstract: Techniques are described herein that are capable of reducing latency of changing an operating state of a processor from a low-power state to a normal-power state. For example, providing a notification from a hardware system to the processor or receiving the notification at the processor, indicating that a transaction layer packet will be provided to the processor at a future time, may trigger the processor to change the operating state from the low-power state to the normal-power state. In another example, receipt of a transaction layer packet at the processor from a hardware system may trigger the processor to change the operating state from the low-power state to the normal-power state.

Abstract: An image recognition device capable of reducing power, a calculation amount, a memory occupancy amount, and a bus band occupancy amount and maintaining high recognition accuracy is provided.

Abstract: A circuit includes, in part, first and second sequential elements and a clock gating circuit. The first sequential element has an enable terminal receiving a first enabling signal, a clock terminal receiving a first clock signal, a data input terminal and a data output terminal. The second sequential element has a clock terminal, and a data input terminal coupled to the data output terminal of the first sequential element. The clock gating circuit is coupled to the first and second sequential elements and includes, in part, a third sequential element configured to store data in response to the first enabling signal and a second enabling signal. The clock gating circuit is further configured to supply a second clock signal to the clock terminal of the second sequential element in response to an assertion of the second enabling signal and the data stored in the third sequential element.

Abstract: Controlling a vehicle comprises: providing, from an activation port, an activation signal for activating control of at least one of one or more electronically controllable devices during a high-speed activation time interval; and managing power consumed by an integrated circuit that includes two or more processor cores during the high-speed activation time interval. The managing includes: receiving the activation signal from the activation port, in response to the activation signal, executing at least a portion of stored code by a first subset of fewer than all of the processor cores at a first power level, and after the high-speed activation time interval, executing at least a portion of the stored code by a second subset of one or more of the processor cores at a second power level lower than the first power level.

Abstract: In an embodiment, a system may include a plurality of component circuits. The plurality of component circuits may include rate control circuits the control power consumption in the component circuits based on indications of power allocated to the component circuits. In an embodiment, the rate control circuits may transmit power requests for the component circuits and a floor request representing a minimum amount of power that may ensure reliable operation.

Abstract: An information processing apparatus and an information processing method capable of fulfilling an image processing function expected in a selected power control mode are provided. The information processing apparatus includes a first processor, a second processor, and a power control unit that determines one power control mode from among a plurality of stages of power control modes different in rated power, and controls power consumption of the first processor and the second processor in the determined power control mode, wherein the power control unit stops an operation of the second processor in response to the determined power control mode being a low power control mode which is a power control mode with the rated power lower than predetermined rated power.

Abstract: A memory device including a receiving circuit is provided. The receiving circuit of the memory device includes a first path receiving a received signal and outputting the received signal directly as a first corrected signal in a current clock signal, a second path holding or tracking the received signal and outputting a second corrected signal in the current clock signal, wherein the second corrected signal is held in a previous clock signal, a summing circuit summing the first corrected signal and the second corrected signal and outputting a summed received signal, and a decision feedback equalizer comparing the summed received signal with a reference signal to decide equalized data and outputting the equalized data in the current clock signal.

Abstract: A first communication device performs a handshaking procedure with a second communication device, the handshaking procedure associated with transitioning from an active mode to a low power mode. The first communication device transmits data and/or idle symbols to the second communication device i) after completion of the handshake procedure, and ii) at least until the earlier of a) a time period expiring, and b) determining that the second communication device quieted a transmitter of the second communication device. The first communication device transitions to the low power mode in connection with the handshaking procedure.

Abstract: Systems, apparatuses and methods may provide for technology that detects an over current condition associated with a voltage regulator in a computing system, identifies a configurable over current protection policy associated with the voltage regulator, and automatically takes a protective action based on the configurable over current protection policy. In one example, the protective action includes one or more of a frequency throttle of a processor coupled to the voltage regulator in isolation from one or more additional processors in the computing system, a deactivation of the processor in isolation from the one or more additional processors, an issuance of a virtual machine monitor notification, an issuance of a data center fleet manager notification, or an initiation of a migration of a workload from the processor to at least one of the additional processor(s).

Abstract: A system comprises a power-over-ethernet (POE) network switch; an intelligent power distribution hub and gateway (IPDHG) configured to communicate with the POE network switch; a rechargeable battery configured to be recharged by the POE network switch; and one or more low duty cycle devices configured to communicate with the IPDHG, wherein the one or more low duty cycle devices are charged by the rechargeable battery.

Abstract: Implementations of this application provide a method and an apparatus for controlling a voltage of a power supply of a data processing device and a data processing device. The method includes: determining a computing power ratio of the data processing device based on an actual computing power and a theoretical computing power of the data processing device; generating a power supply control instruction based on a result of comparison between the computing power ratio and a predetermined threshold; and controlling an output voltage of the power supply of the data processing device based on the power supply control instruction. According to the implementations of this application, the output voltage of the power supply is controlled according to the computing power ratio, and a good compromise can be obtained between the power consumption loss and the computing power of the data processing device.

Abstract: An electronic apparatus includes a first component and a second component. The first component is configured to connect to a processing device containing a power storage module, and the second component is configured to connect to an extension device. In a first state, the electronic apparatus connects to the processing device and the expansion device. An external power supply provides power to the processing device through the first component, and provides power to the expansion device. In a second state, the electronic apparatus connects to the processing device and the expansion device. In response to the external power supply being cut off, power is supplied to the expansion device through the second component. The processing device is powered by its power storage module. After the electronic apparatus switches from the first state to the second state, the connection state of the expansion device and the processing device is capable of being maintained.

Abstract: An information handling system may include a processor and a basic input/output system communicatively coupled to the processor and comprising a program of executable instructions configured to determine a context associated with a current boot session of the information handling system and based on user boot history stored during one or more previous boot sessions of the information handling system and the context, load one or more network drivers necessary to boot the information handling system in accordance with the context.

Abstract: A storage unit is disclosed. The storage unit may include an interface to a host and storage for a data. A receiver may receive from a host a boot power data. The boot power data may including a first power level and a duration. A circuit may boot the storage unit based at least in part on the boot power data. The storage unit may include a second power level, with the first power level greater than the second power level.

Abstract: Techniques are provided for managing power to various devices within a suite or room, such as an operating room. In an example, an apparatus can include a first input configured to couple to a system controller of an operating room, multiple outputs configured couple to control inputs of one or more power relays, and a controller configured to control the one or more power relays via the multiple outputs in response to a power status of the system controller. The first input can be indicative of the power status of the system controller. Each power relay of the one or more power relays can be configured to selectively connect power to medical equipment of the operating room.