Abstract: This application relates to techniques that adjust the sleep states of a computing device based on proximity detection and predicted user activity. Proximity detection procedures can be used to determine a proximity between the computing device and a remote computing device coupled to the user. Based on these proximity detection procedures, the computing device can either correspondingly increase or decrease the amount power supplied to the various components during either a low-power sleep state or a high-power sleep state. Additionally, historical user activity data gathered on the computing device can be used to predict when the user will likely use the computing device. Based on the gathered historical user activity, deep sleep signals and light sleep signals can be issued at a time when the computing device is placed within a sleep state which can cause it to enter either a low-power sleep state or a high-power sleep state.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to reduce temperature of a networked device. An example apparatus includes, a temperature threshold monitor to identify a temperature condition associated with the device, a window information retriever to retrieve a current value of a network receive capacity parameter, and a window adjustor to reduce the temperature of the device by generating a modified network receive capacity parameter, the modified network receive capacity parameter based on a ratio of the current value of the network receive capacity parameter and a decrease factor.

Abstract: A power source device coupled to a power device includes an output port and a controller. When the output port is coupled to a connection cable, the controller is activated to generate a handshake signal, so as to communicate with the power device. When it is determined that the power device is able to be powered according to the handshake signal, the controller controls the power supply device to power the power device through the connection cable. When the connection cable is not coupled to the output port, the controller is deactivated and thus the handshake signal is not generated.

Abstract: An information handling system includes a processor complex and a baseboard management controller (BMC). The processor complex provides boot status information in response to a system boot process of the processor complex. The BMC receives first boot status information from the processor complex in response to a first system boot process, compares the first boot status information to baseline status information to determine first boot status difference information, compares the first boot status difference information to baseline boot status difference information to determine that the information handling system experienced an anomaly during the first system boot process, and sends an alert that indicates that the first system boot process experienced the anomaly.

Abstract: The present disclosure provides an electronic device including a main controller and a communication controller configured to communicate with the main controller and a device through a predetermined physical communication interface based on a predetermined communication standard. The communication controller instructs power-off of the predetermined physical communication interface and the device when an event which causes transition to a power saving state occurs in the main controller, and determines whether the predetermined physical communication interface is to be returned from the power saving state without power-on of the device or with power-on of the device when an event which causes return from the power saving state occurs in the main controller.

Abstract: In an embodiment, a processor includes a plurality of processing engines to execute instructions and a power management unit. The power management unit is to: control an operating frequency and a supply voltage according to a first voltage/frequency curve associated with a first temperature; and in response to a detection of a second temperature in the processor, increase the operating frequency to a second frequency based on a second voltage/frequency curve, wherein, at least one voltage of a first range of voltages, the second voltage/frequency curve specifies a higher frequency than the first voltage/frequency curve. Other embodiments are described and claimed.

Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

Abstract: Embodiments may include systems and methods for communication including a communication port with a first lane and a second lane, a first power controller and a second power controller coupled to the communication port. The first power controller is to control, at a first time instance, the first lane to operate in a first power state selected from a first set of power states for the first lane. The second power controller is to control, at a second time instance, the second lane to operate in a second power state selected from a second set of power states for the second lane, wherein the first power state is different from the second power state. Other embodiments may be described and/or claimed.

Abstract: Embodiments of the present invention provide methods and apparatus for metering GPU workload in real time. Metering of the GPU workload is performed by a Workload Metering (WLM) algorithm implemented in software or firmware that calculates a duty cycle for the graphics engine. The duty cycle forces the graphics engine to transition from a busy state to an idle state periodically based on measured power consumption, and engages race-to-sleep techniques to place the engine or engines in a low power state during the forced idle times, thereby reducing the overall power draw of the GPU to meet a predetermined power budget. According to some embodiments, the WLM algorithm is deployed on a microcontroller of a power management unit (PMU).

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Abstract: A method for secure data communications using an insecure protocol, comprising generating a data message at a data processor client. Adding a security key to the data message using the data processor client. Transmitting the data message to a remote data processor receiver over a data network. Determining whether the data message is authentic at the remote data processor receiver. Automatically responding to the data message with a location where additional data can be obtained from the remote data processor receiver if it is determined by the remote data processor receiver that the data message is authentic.

Abstract: A processing method and a terminal device are provided. The processing method comprises, provided that a storage device stores an association relationship between a first communication identifier and a first device identifier corresponding to a terminal device, and the terminal device is not connected to the storage device, monitoring whether a predetermined condition is satisfied. The processing method further comprises, in response to monitoring that the predetermined condition is satisfied, performing a corresponding process. After the terminal device and the storage device are connected, the storage device stores an association relationship between a second communication identifier and a device identifier corresponding to the terminal device.

Abstract: An apparatus includes an external terminal, an output circuit having an impedance corresponding to a code signal, and a calibration circuit configured to produce the code signal responsive to a comparison of a voltage at the external terminal with a reference voltage, the comparison performed by a first cycle period in a first mode and by a second cycle which is longer than the first cycle period in a second mode.

Abstract: A radio module, radio module, comprising a battery; and a radio circuit, the radio circuit comprising: a DC-to-DC converter coupled with the batters and configured to convert a battery voltage to a first DC voltage level; at least one regulator coupled with the DC-to-DC converter and configured to covert the first DC voltage level to a second DC voltage level; a plurality of circuit blocks coupled with the at least one regulator such that the second DC voltage level is configured to provide power to the plurality of circuit blocks; a real time clock configured to provide a clock signal to the plurality of circuit blocks; and a management unit coupled with the plurality of circuit blocks and configured to implement a state machine to control the plurality of circuit blocks, wherein the state machine causes the management unit to cause the second DC voltage level to be applied to and removed from at least some of the plurality of circuit blocks during various states comprising the state machine, wherein the plu

Abstract: Technology to dynamically share system power among charging ports of a multiport power delivery (PD) system is described. In one embodiment, a multiport PD system includes a master controller associated with a master port, and one or more slave controllers associated with one or more slave ports. The master controller determines a port connection status of a set of multiple ports. The port connection status indicates that multiple devices are connected. The master controller determines a power requirement of each of the devices. The master controller dynamically allocates a system power between each of the ports, independent of a connection sequence of the devices.

Abstract: A method of determining a time stamp for an event in a digital processing system, the method comprising the steps of: obtaining a coarse time stamp from a time stamp counter; obtaining timing correction data from one or more hardware components of the system; and adjusting the coarse time stamp value based on the timing correction data to provide a precision time stamp value.

Abstract: A computing device, such as a multifunction printer, may be configured to supply electrical power to one or more external devices. The computing device may include a user interface that can display information to a user, informing the user of the electrical power being supplied to the one or more external devices and/or of the total amount of electrical power that is available to the one or more external devices. The user may use the user interface to adjust the amount of power being supplied to each of the external devices, and the computing device may store information indicating the user's adjusted power levels and use the stored information to control the amount of power supplied to the external devices.

Abstract: A method for a network apparatus to control power provision to a powered device is proposed. The network apparatus is configured for connection to the powered device, an electronic device, and a power supply device. The network apparatus permits transmission of electronic power provided by the power supply device to the powered device therethrough when the electronic device is communicatively connected to the network apparatus, and does not permit transmission of electronic power provided by the power supply device to the powered device therethrough when the electronic device is not communicatively connected to the network apparatus.

Abstract: A hierarchy of interconnected memory retention (MR) circuits detect a clock gating mode being entered at any level of an integrated circuit. In response, the hierarchy automatically transitions memory at the clock gated level and all levels below the clock-gated level from a normal operating state to a memory retention state. When a memory transitions from a normal operating state to a memory retention state, the memory transitions from a higher power state (corresponding to the normal operating state) to a lower power state (corresponding to the memory retention state). Thus, in addition to the dynamic power savings caused by the clock gating mode, the hierarchy of MR circuits automatically transitions the memory modules at the clock gated level and all levels below the clock gated level to a lower power state. As a result, the leakage power consumption of the corresponding memory modules is reduced relative to prior approaches.

Abstract: An information processing apparatus includes a wired electric power supply connector configured for connection with a wired electric power supply to receive electric power therefrom, non-contact electric power supply connector configured for electric coupling with a non-contact electric power supply to receive electric power therefrom, and a processor. The processor selects, for electric power supplied to each component of the information processing apparatus, one of the wired electric power supply and the non-electric power supply, wherein the wired electric power supply is selected at a time of startup of the information processing apparatus, and the non-contact electric power supply is selected if an operation state of the information processing apparatus or the non-contact power supply meets a predetermined condition. The processor controls the wired electric power supply connector and the non-contact electric power supply connector to supply electric power to each component based on the selection.