Abstract: Systems and methods of controlling signal polarization are provided herein. An antenna array may include antenna elements each communicatively connected to a variable gain amplifier (VGA) with discrete amplitude control, and a phase shifter with discrete phase control, to provide discrete polarization states. A polarization controller may identify a target polarization state with a target amplitude and a target polarization angle. The polarization controller may identify a first polarization state and a second polarization state from the discrete polarization states, that are nearest in absolute amplitude to the target amplitude and nearest in polarization angle to the target polarization angle. The polarization controller may concurrently form a signal with the identified first polarization state using a first portion antenna elements, and a signal with the identified second polarization state using a second portion of antenna elements.

Abstract: According to an embodiment of the present disclosure, an electronic device may comprise a memory and a processor configured to produce compressed data by compressing data including a first block and a second block stored in the memory, wherein the processor may be configured to include a first replacement data table corresponding to first sub-data in the compressed data, the first sub-data included in the first block, and the first replacement data table produced based on, at least, rankings of first frequencies for the first sub-data, and include information for reference to the first replacement data table, corresponding to the second block, when second sub-data included in the second block and rankings of second frequencies for the second sub-data meet a designated condition with respect to the first sub-data included in the first block and the rankings of the first frequencies. Other embodiments are also possible.

Abstract: A digital to time converter (DTC) system is disclosed. The DTC system comprises a DTC circuit configured to generate a DTC output clock signal at a DTC output frequency, based on a DTC code. In some embodiments, the DTC system further comprises a calibration circuit comprising a period error determination circuit configured to determine a plurality of period errors respectively associated with a plurality consecutive edges of the DTC output clock signal. In some embodiments, each period error of the plurality of period errors comprises a difference in a measured time period between two consecutive edges of the DTC output clock signal from a predefined time period. In some embodiments, the calibration circuit further comprises an integral non-linearity (INL) correction circuit configured to determine a correction to be applied to the DTC code based on a subset of the determined period errors.

Abstract: Methods of code conversion are provided. Aspects include obtaining a first code point from a source data string in a first character encoding, wherein the source data string is to be converted to a target data string in a second character encoding. A target code point corresponding to the first code point is looked up in a map table, wherein the target code point is in the second character encoding. It is determined whether the first code point is a first combining character in response to receiving a lookup failure generated from the looking up operation. A combination unit having the first combining character and a base character next to the first combining character in the source data string is identified in response to determining that the first code point is the first combining character. The combination unit is converted to a substitute character in the target data string.

Abstract: An antenna structure includes a first ground element, a feeding element, a shorting element, a parasitic tuning element, a second ground element, a first parasitic element, a second parasitic element, and a dielectric substrate. The feeding element is coupled through the shorting element to the first ground element. The parasitic tuning element is coupled to the first ground element. The parasitic tuning element is at least partially surrounded by the feeding element, the shorting element, and the first ground element. The second ground element is adjacent to the feeding element. The first parasitic element and the second parasitic element are coupled to the second ground element. The feeding element, the shorting element, the parasitic tuning element, the first parasitic element, the second parasitic element, and at least one of the first ground element and the second ground element are disposed on the dielectric substrate.

Abstract: A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2n representation of the numerical value to be coded, wherein “n” is a natural number equal to or greater than 1.

Abstract: An analog-to-digital conversion method and an A/D conversion device for a temperature sensor are provided. An analog front-end circuit generates an A/D converter input signal positively correlated to a temperature and an A/D converter reference voltage signal negatively correlated to the temperature, and an operation is performed on a ratio of amplitudes of the generated signals to obtain a quantized output value. Since the amplitude of the A/D converter input signal is less than that of the A/D converter reference voltage signal, measurements on other signals is compatible with the measurement on the temperature in a multi-sensor system. A digitized output value is calculated by a digital-assisted readout method to generate a linear output relating to a temperature, thereby improving the accuracy of temperature measurement and reducing complexity of analog circuit design.

Abstract: An image sensor may contain an array of imaging pixels arranged in rows and columns. Each column of imaging pixels may be coupled to a column line which is used to read out imaging signals from the pixels. The column line may be coupled to an analog-to-digital converter for converting analog imaging signals from the pixels to digital signals. The analog-to-digital converter may be implemented as a charge sharing successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include a comparator coupled to a feedback digital-to-analog converter (DAC). The comparator may have a non-zero comparator offset. The feedback DAC may include capacitors that are scaled using a sub-radix-2 sizing scheme to help improve tolerance to the comparator offset while enabling resolutions of up to 10-bits or more.

Abstract: An electronic device includes a housing. The housing defines a slot and a groove communicating with the slot. The housing is divided into at least a first radiating portion and a second radiating portion by the slot and the groove. The first radiating portion is spaced apart from the second radiating portion. The first radiating portion and the second radiating portion cooperatively serve as an antenna structure of the electronic device to receive and/or transmit wireless signals. The electronic device further performs a predetermined function through the groove.

Abstract: Dither circuitry includes harmonic signal generation circuitry configured generate a high order even harmonic of a base excitation signal. The dither circuitry also includes a combiner configured to generate a dithered excitation signal based on the high order even harmonic and the base excitation signal. The dither circuitry further includes an output terminal configured to output the dithered excitation signal to a sensor device.

Abstract: Pipelined analog-to-digital converters (ADCs) include a flash ADC that reduces noise tones in power supply current drawn by the flash ADC. A pipelined analog-to-digital converter (ADC) includes a flash ADC and error correction circuitry coupled to the flash ADC. The flash ADC includes a plurality of latched comparators and a plurality of driver circuits. Each of the latched comparators includes an inverting output and a non-inverting output. Each of the driver circuits is coupled to one of the latched comparators, and includes an input terminal and an output terminal. In a first subset of the driver circuits the input terminal is coupled to the inverting output of one of the latched comparators. In a second subset of the driver circuits the input terminal is coupled to the non-inverting output of one of the latched comparators.

Abstract: Apparatus comprises data compression circuitry to process a set of data values, the data compression circuitry comprising: detector circuitry to detect, for each of n complementary groups of m data values of the set of data values, a first subset of the groups for which the data values in the group have a predetermined pattern of data values, where m and n are integers and m×n is the number of data values in the set of data values; generator circuitry to generate a compressed data packet comprising at least: a representation of a second subset of the groups, the second subset being each of then complementary groups other than groups in the first subset; and an indication of a group position, with respect to the set of data values, of each group in the second subset of groups. Complementary decompression apparatus is also described.

Abstract: A time-to-digital converter is provided. The time-to-digital converter comprises an oscillator controller, an invertible oscillator and a measurement circuit. The oscillator controller receives a start signal and a stop signal and outputs a mode signal. The invertible oscillator is electrically connected with the oscillator controller for receiving the mode signal. The oscillation direction of the invertible oscillator is inverted according to the mode signal, and the invertible oscillator outputs plural delay signals. The measurement circuit is electrically connected with the invertible oscillator for receiving the plural delay signals. The measurement circuit receives a sampling signal, samples the plural delay signals in accordance with the sampling signal, and outputs an output signal.

Abstract: Circuits for a successive approximation register analog-to-digital converter and related methods. A global reference circuit includes a first super source follower (SSF) circuit having an input coupled to an output of a first current mirror and to a first adjustment circuit, and an operational amplifier having an input coupled to an output of the first SSF circuit and an output coupled to an input of the first current mirror. Local slices each include a second current mirror having an input coupled to the output of the operational amplifier, a second super source follower (SSF) circuit having an input coupled to an output of the second current mirror and to a second adjustment circuit. The first and second adjustment circuits may be configured to adjust a voltage at the input of the first SSF circuit and respective voltages at the input of the second SSF circuit of each local slice.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: An antenna structure includes a feed portion, a high-frequency radiating portion, a low-frequency radiating portion, an extension portion, and a switching unit. The high-frequency radiating portion is electrically connected to the feed portion. The low-frequency radiating portion is electrically connected to the high-frequency radiating portion. The extension portion is electrically connected to the feed portion and the high-frequency radiating portion. The switching unit is electrically connected to the extension portion to control the extension portion to be in one of an open-circuit state and a short-circuit state.

Abstract: Technique for improving efficiency of on-chip antennas, comprising placing each antenna on an individual area on the chip, defined by channels provided in the chip before or after placing the antenna(s). The channels may be metallized. Frequency of a radiating antenna element may be locked by wireless injection locking using a locked subharmonic frequency.

Abstract: A method for compressing digital data, including: extrapolating a value of each sample of data to be compressed as a function of a value of at least one preceding sample, to produce an extrapolated sample; differentiating between each extrapolated sample and the corresponding sample of data to be compressed, to produce a differentiated sample; and deleting redundancy between successive differentiated samples produced by the differentiating stage.

Abstract: An antenna (100) enables improved multi-band operation for a portable communication device, such as a portable two-way radio. The antenna structure is formed of a first radiator element (104) fed through a single radio frequency (RF) feed port (118) and terminated on the input of a transmission line (108). The transmission line (108) is routed along a ground plane reference mass (102) towards a second radiator element (106). Applying the antenna structure to a radio embodiment, the first radiator element (104) is placed at a bottom side of a portable radio device, the first radiator element being fed through the single RF feed port and terminated on the input of the transmission line. The transmission line is routed along the ground plane reference mass towards the second radiator element placed on a top side of the portable radio.

Abstract: The present invention provides a continuous-time delta-sigma modulator comprising two ADCs. One of the ADC is configured to generate MSBs of an output signal of the continuous-time delta-sigma modulator, and the other ADC is configured to generate LSBs of the output signal. In addition, the two ADCs sample an output of a loop filter at different times, but the MSBs and LSBs are feedback to the loop filter simultaneously.