Abstract: There provided an AD converter that includes an analog processing part configured to select one of the measurement target voltages and a plurality of reference voltages for each channel, to output an analog voltage signal; a first selection part configured to select one of a plurality of analog voltage signals; a first AD conversion part configured to perform AD conversion on the analog voltage signal to generate a first original digital signal; a second selection part configured to select one of the plurality of analog voltage signals; a second AD conversion part configured to perform AD conversion on the analog voltage signal to generate a second original digital signal; a digital processing part configured to receive the first original digital signal and the second original digital signal; and a controller configured to control contents selected in the analog processing part, the first selection part, and the second selection part.

Abstract: A system includes analog-to-digital converter (ADC) logic, wherein the ADC logic includes a stage with a dynamic comparator circuit. The ADC logic also includes a residue stage. The dynamic comparator circuit includes a preamplifier and a common mode clamp circuit for the preamplifier.

Abstract: An Analog to Digital (ADC) is provided, where the ADC may include a sample and hold circuitry to sample an analog input signal, and a summation block to iteratively generate a subtraction signal. The subtraction signal may be based on a difference between the analog input signal and a feedback signal. The ADC may further include a common input stage to receive the subtraction signal, and a plurality of comparison and latch circuitries arranged in parallel, where individual ones of the plurality of parallel comparison and latch circuitries may sequentially receive an output of the common input stage.

Abstract: Provided is an integrated circuit including an analog-to-digital converter (ADC) configured to convert an analog signal to a digital signal; and a digital signal processor (DSP) configured to process the digital signal, wherein the ADC generates a power source during a process for converting the analog signal into the digital signal and supplies power to the DSP through the power source.

Abstract: A DAC device includes a first DAC circuit and a second DAC circuit. The first DAC circuit includes multiple DAC portions, each of which includes multiple pMOSFETs. The second DAC circuit includes multiple DAC portions, each of which includes multiple nMOSFETs. For each of the first and second DAC circuits, bulk terminals of at least some of the MOSFETs of each DAC portion are for receiving a respective one of bulk voltages with different magnitudes, a gate terminal of each of the MOSFETs of the DAC portions is for receiving a gate signal, and voltage magnitudes of at least some of the gate signals received by each DAC portion switch between a respective one of different logic high levels and a respective one of different logic low levels.

Abstract: A method and apparatus of entropy coding for a video encoder or decoder using multiple-table based Context-Based Adaptive Binary Arithmetic Coder (CABAC) are disclosed. In one embodiment, a current bin of a binary data of a current coding symbol is encoded or decoded according to a probability of a binary value of the current bin and the probability of the binary value is updated according to the binary value of the current bin for a next bin by using multiple-parameter probability models. Each multiple-parameter probability model is updated using at least one lookup table with the individual set of probability state as a table index to access contents of said at least one lookup table. In another embodiment, the range update is calculated for a range interval based on middle value of the range interval.

Abstract: A comparator offset voltage self-correction circuit is disclosed. A comparator offset voltage which is caused by the semiconductor process parameter randomness also has randomness. Due to the randomness of the comparator offset voltage, a reference voltage of a parallel comparator in a parallel-conversion-type analog-to-digital converter is uncertain. If the comparator offset voltage is large, the parallel-conversion-type analog-to-digital converter may even have a functional error. The comparator offset voltage self-correction circuit provided in the present invention can correct a random offset voltage of a comparator to meet requirements.

Abstract: An apparatus such as an electronic circuit includes an input operable to receive an input signal; a dynamic common mode adjustor operable to: i) derive a differential signal from the received input signal, and ii) control an offset of the differential signal as a function of the received input signal to produce an offset differential signal; and an output operable to output the offset differential signal. In one arrangement, the offset differential signal outputted from the output includes a first signal and a second signal; a difference between the second signal and the first signal proportionally varies with respect to the received input signal.

Abstract: A first value of a first data element in a first set of data elements is obtained, the first set of data elements being based on a first time sample of a signal. A second value of a second data element in a second set of data elements is obtained, the second set of data elements being based on a second, later time sample of the signal. A measure of similarity is derived between the first value and the second value. Based on the derived measure, a quantisation parameter useable in performing quantisation on data based on the first time sample of the signal is determined. Output data is generated using the quantisation parameter.

Abstract: Time-to-digital conversion circuitry converts a time between a start time point and a stop time point, which are state-change time points of digital signals, into digital. The time-to-digital conversion circuitry comprises oscillation circuitry that outputs a plurality of phase signals having different phases, and outputs a digital value of the time based on the plurality of phase signals. The oscillation circuitry performs free-running oscillation and outputs the phase signals that do not synchronize with the start time point and the stop time point.

Abstract: This invention discloses a successive approximation register analog-to-digital converter (SAR ADC) and a control circuit thereof. The SAR ADC includes a comparator, a switched-capacitor digital-to-analog converter (DAC), and a control circuit. The switched-capacitor DAC includes a capacitor and a driving circuit that is electrically connected to the capacitor. The driving circuit comprises a P-type MOSFET and an N-type MOSFET, and the gates of the two MOSFETs are not electrically connected. The P-type MOSFET is controlled by a first control signal, and the N-type MOSFET is controlled by a second control signal. The control circuit controls the voltage at one end of the capacitor to switch from a high voltage level to a low voltage level by controlling the rising edge of the first control signal to lead the rising edge of the second control signal.

Abstract: A digital delta-sigma modulator may include a loop filter having a loop filter input configured to receive an input signal and generate an intermediate signal responsive to the input signal and a multi-bit quantizer configured to quantize the intermediate signal into a quantized output signal which is fed back as an input to the loop filter. The multi-bit quantizer may further be configured to operate in at least two modes comprising: (a) a normal mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a set of a plurality of quantization levels; and (b) a code suppression mode in which, for each sample of the intermediate signal, the multi-bit quantizer generates a corresponding sample having a value selected from a subset of the set of a plurality of quantization levels.

Abstract: Neural network circuits providing early integration before ADC are described. Comparators are adapted to compare a plurality of output analog voltages from a first synaptic array to a predetermined threshold to generate a vector of bits indicating whether the plurality of analog voltages exceed the predetermined threshold, and transmit the vector of bits via a network. At least one ADC is configured to convert the plurality of analog voltages to a vector of digital values, and transmit the vector of digital values via the network. At least one modulator is configured to receive the vector of bits from the network, provide pulses to each of a plurality of input wires of a second synaptic array based on the vector of bits, receive the vector of digital values from the network, and provide pulses to each of the plurality of input wires based on the vector of digital values.

Abstract: Disclosed examples include a segmented DAC circuit, including an R-2R resistor DAC to convert a first subword to a first analog output signal, an interpolation DAC to offset the first analog output signal based on an N-bit digital interpolation code signal to provide the analog output signal, and a Sigma Delta modulator to modulate a modulator code to provide the N-bit digital interpolation code signal that represents a value of second and third subwords.

Abstract: Circuits for an analog-to-digital converter and methods of operating an analog-to-digital converter. A resistor digital-to-analog converter (RDAC) has a first reference node coupled to a first current source, a second reference node coupled to a second current source, an input port configured to receive a first voltage, and an output port coupled to a buffer. The RDAC is configured to generate a second voltage including a first voltage shift from the first voltage and to supply the second voltage from the output port of the RDAC to the buffer.

Abstract: A voltage-mode digital-to-analog converter (DAC) includes input circuitry and an array of output impedance units disposed in parallel. The input circuitry receives a digital word of N bits. A selectable number of the output impedance units are activated to produce a desired aggregate output impedance. The selectable number is free to be a number different than N.

Abstract: Increasing a dynamic range of a digital to analog converter (DAC). A signal analysis element is positioned prior to the DAC in a processing path. The element evaluates an instantaneous amplitude of a signal to be applied to the DAC. The DAC is capable of a first full scale value. An additional current source supports a second full scale value of the DAC, which is greater than the first full scale value. Upon the element determining that a condition is not satisfied, the element employs current steering to couple the additional current source to a current sink. However, upon the element determining that the condition is satisfied, the element employs current steering to couple the additional current source to an output of the DAC to support the second full scale value of the DAC.

Abstract: A integrated circuit device includes digital-to-analog converter (DAC) circuitry including a resistor DAC that includes a resistor-two-resistor DAC configured to receive a first sub-word that includes a most significant bit (MSB) of a digital input signal and to output an analog output signal representative of the first sub-word, a resistor ladder configured to receive the analog output signal and a second sub-word that includes an intermediate significant bit (ISB) of the digital input signal and to generate an analog interpolated signal. The resistor ladder includes a plurality of resistor elements connected in series with one another to define a plurality of tap nodes, wherein a respective tap node is arranged between every two adjacent ones of the resistor elements, and a switching circuit having plurality of switches, wherein each switch is configured to selectively connect a respective one of the tap nodes to an output of the resistor ladder to generate the analog interpolated signal.

Abstract: A method and an apparatus for determining the suitability of a test delay value between comparator decisions of a comparator circuit of an asynchronous successive approximation analog/digital converter and a method for determining an optimized delay value of a comparator of an asynchronous successive approximation analog/digital converter are provided.

Abstract: A circuit for digital-to-analog conversion using a plurality of 3-level cells includes a circuit for digital-to-analog conversion using a plurality of 3-level cells mutually independently providing positive electricity, providing negative electricity, or floating. The circuit including a preprocess circuit and a shift circuit. The preprocess circuit is configured to receive thermometer code data generated from signed binary data and generate a shift count for shifting a cell pointer pointing to one of the plurality of 3-level cells for dynamic element matching (DEM) from the thermometer code data. The shift circuit is configured to store the cell pointer and shift the stored cell pointer according to the shift count. The shifted cell pointer is shifted in proportion to an absolute value of the binary data in a direction depending on a sign of the binary data.