Abstract: Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

Abstract: Embodiments include exerciser device placement in the development of an integrated circuit. Aspects of the invention include obtaining a design of an integrated circuit and creating a dynamic power blockage map for the integrated circuit. Aspects also include updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map. Based on a determination that the updated integrated circuit design complies with one or more design constraints, aspects further include outputting the updated integrated circuit design.

Abstract: Embodiments including a semiconductor device circuit for biasing gates of a qubit device as well as a method for operating the device are disclosed. The embodiments may include a multiplexed array of capacitor cells, where each capacitor cell includes a transistor-controlled capacitor, where each capacitor is connected between a drain of a respective transistor and ground, where each source of all transistors of all capacitor cells are connected to a common control point, and where each gate of the transistors of the capacitor cells are individually voltage controllable. The embodiment may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternatively activatable.

Abstract: The present disclosure relates to a computer-implemented method for automatically partitioning an electronic design. Embodiments may include accessing, using the at least one processor, the electronic design and partitioning the electronic design using a multi-mode partitioning methodology. Embodiments may further include defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies and performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

Abstract: An apparatus comprising a crystal; at least three first wires arranged substantially parallel to each other; at least two second wires arranged substantially parallel to each other, each second wire arranged non-parallel to each first wire, such that each second wire crosses each first wire, forming at least six cross points; and at least six colour centres, each colour centre located within the crystal adjacent a different one of the at least six cross points.

Abstract: The present invention discloses an inverse design method of an on-chip filter based on equivalent circuit space mapping, and belongs to the technical field of radio frequency integrated circuits. According to the present invention, based on an equivalent circuit model, a nonlinear relationship between performance parameters and structure parameters of a CMOS millimeter-wave filter is divided into two parts, namely, a part of realizing mapping from performance parameters to equivalent circuit element values by virtue of an odd and even mode theory; and a part of establishing an artificial neural network (ANN) model, in which input vectors are the equivalent circuit element values and output vectors are the structure parameters. By space mapping in the design of the present invention, the defect of discretized sampling of the scattering parameters in a traditional modeling design method is avoided; and compared with forward optimization, the required design time can be significantly shortened.

Abstract: Provided are an optical proximity correction (OPC) method capable of addressing the limitations of patterning and improving the reliability of patterning, and a mask manufacturing method using the OPC method. In the OPC method, a rectangular mask layout for a target pattern is created, the edge of the rectangular mask layout is dissected into segments, a first shape variable point is created, and a second shape variable point is created by shifting the first shape variable point on a rounded target pattern. Thereafter, a curvilinear mask layout is created based on the second shape variable point, a contour is extracted based on the curvilinear mask layout, an edge placement error (EPE) is determined, and the operations are repeated according to a predetermined criterion, thereby realizing a mask layout with minimal EPEs.

Abstract: A method of determining a quantum operation control layout for a quantum computation on a quantum system is provided. The quantum computation is to be carried out on constituents of the quantum system arranged in accordance with a mesh. Vertices of the mesh represent possible sites for the constituents of the quantum system. Each cell of the mesh indicates that quantum interactions between constituents of the quantum system arranged in that cell are possible during the quantum computation. The method includes providing a data set including data representing hyperedges of a hypergraph. The method includes determining a set of generalized cycles. The method includes determining a mesh mapping that maps data representing the hyperedges of the hypergraph or of the enlarged hypergraph to the vertices of the mesh. The method includes generating the quantum operation control layout. The quantum operation control layout includes data indicating layout vertices of the mesh.

Abstract: Systems, methods and apparatus for wireless charging are disclosed. A wireless charging device has a resonant circuit including one or more power transmitting coils in a charging surface of the charging device, a driver circuit configured to provide a charging current to the resonant circuit, and a controller. The controller is configured to determine an average transmitted power using samples of current and voltage captured from the resonant circuit, and determine that a foreign object is located on or near the charging surface when the average transmitted power exceeds a measurement of received power provided by a receiving device and parasitic losses associated with the wireless charging device. In one example, each sample of current is obtained by measuring a current flowing in the resonant circuit, and each of sample of voltage is obtained by measuring a voltage across the one or more power transmitting coils.

Abstract: A universal base for an electric toothbrush has a body comprising a top surface, a bottom surface, and a side surface therebetween. The base can be coupled with the toothbrush for wireless communication therebetween. The base includes a charging component for inductively charging the electric toothbrush, a Bluetooth component for communicating usage data received from the toothbrush during a brushing session, an analyzing component for instantaneous processing of the usage data received from the toothbrush, a timer-clock component for displaying either a count-up or a countdown of the brushing session during the brushing session and time of day before and after the brushing session, and a multi-functional light component for instantaneously communicating, during the brushing session, at least one element of the usage data.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, the apparatus includes memory, instructions, and processor circuitry to instantiate or execute the machine readable instructions to determine a design block associated with a design exception, parse the design block into a functional netlist of cell families, generate a cell occurrence counts distribution, and group cell families into cell family bins corresponding to fabrication parameters. The processor circuitry further determines inclusion of a first cell family bin does not improve one or more process technology attribute values and causes a user interface to indicate the first cell family bin as a cell family bin candidate for removal from the functional netlist.

Abstract: A method of modifying a layout for an integrated circuit (IC) includes: selecting, in the layout, a circuit region to be scaled; setting a fixed area including a fixed feature in the selected circuit region; and scaling the selected circuit region, without scaling the fixed area including the fixed feature, to obtain a modified layout for the IC.

Abstract: The present disclosure relates to a mobility system and an update management method thereof. An exemplary embodiment of the present disclosure provides a mobility system including: one or more controllers; one or more batteries; and an update management apparatus configured to determine an order of update target controllers and a battery to supply power to the update target controllers by using at least one of relative importance of the one or more controllers, a present state of the one or more batteries, or a vehicle driving state.

Abstract: An electronic design automation (EDA) tool and system for physical verification of workflow for semiconductor circuit designs, and methods of using the same is described. Generally, the method includes (i) automatic splitting an integrated circuit (IC) layout into a number of windows for parallel processing using a plurality of central processing cores; (ii) extracting parasitic capacitance structures from the IC layout; (iii) generating fill elements for masks to fabricate an IC having the IC layout using a metadata matrix to minimize volume of information and resources needed; and (iv) extraction of parasitic resistance structures from IC layout. In some embodiments, the IC layout is additionally or alternatively split into groups of rules for processing. Other embodiments are also described.

Abstract: Various examples are provided for high voltage isolation. The isolation can be provided for discrete non-isolated devices using an electrically isolating substrate that is thermally conductive. In one example, a module includes a plurality of switching devices connected in series; one or more rubber buffer disposed between switching device pairs of the plurality of switching devices; and thermal interfaces disposed between switching devices of the switching device pairs and cooling surfaces of the module, the thermal interfaces electrically isolating the switching devices from the cooling surface. In another example, an extreme fast charger (EFC) station includes an active front end (AFE) module that includes at least one module, where the module is a half-bridge power module. The EFC station can include a dual-active-bridge (DAB) high voltage (HV) module that includes at least one module, where the module is a half-bridge power module.

Abstract: An under-floor charging station can be mounted under a floor such that a top plate of the under-floor charging station is substantially flush with a top surface of the floor without touching the ground. Openings in the top plate allow charging elements to extend when in use to charge a mobile robot, and to retract under the floor when not in use. The retractable charging elements prevent tripping hazards and allow the mobile robot to move freely throughout a clean room. Moreover, because the charging elements can be retracted in an unobtrusive position when the under-floor charging station is not in use, the under-floor charging station is permitted to be positioned in locations in the clean room that allow the mobile robot to continue working while charging and/or allow non-stop running of the mobile robot.

Abstract: An information handling system includes a processor, a memory device, a PMU to provide power to the processor and memory device, and a battery operatively coupled to the PMU.

Abstract: A system for coupling a qubit to a register, wherein the system controls application of a protocol comprising a sequence of pulses synchronized with an RF field, the protocol further comprising a timing, a phase, and a duration of each of the pulses comprising a single qubit gate, a period and amplitude of the RF field, and a number of repeats of the sequence, so that application of the protocol controls a coherent spin exchange interaction between a register and a qubit having a zero magnetic dipole moment. The qubit comprises a first spin state and a second spin state both of which have a zero magnetic dipole moment; the register comprises multiple register spins having an energy level structure; and the register spins are indistinguishable so as to be configurable in basis states including a superposition state used for storing the quantum state of the qubit.

Abstract: A wireless charging system includes a hollow electromagnetic waveguide and a platform that, when placed inside the waveguide, positions one or more wireless devices to absorb energy from an electromagnetic field propagating along the waveguide. The system also includes first and second couplers located near opposite ends of the waveguide. The first coupler, when driven with an electrical signal, couples energy from the electrical signal into the electromagnetic field. At the same time, the second coupler couples energy from the electromagnetic field into an electrical receiving signal. The second coupler may be connected to a dissipative load to dissipate the energy of the electrical receiving signal. Alternatively, the electrical receiving signal can be processed to power the wireless charging system. The wireless charging system charges the wireless devices with high efficiency regardless of their positions inside the waveguide, thereby ensuring that the wireless devices charge at a similar rate.