Abstract: The present disclosure describes a system and method for determining a function for a quality of results (QoR) for a circuit design. The method includes receiving a circuit design that includes a first node, a second node, and a connection between the first node and the second node in a design space, placing an array of points within the design space, sampling first field values of the circuit design at each point of the array of points, and determining a first sampled function based on the first field values. The method includes moving the array of points within the design space, sampling second field values of the circuit design at each point of the array of points, determining a second sampled function based on the second field values, and determining a function based on the first and second sampled functions. The function produces a QoR for the circuit design.

Abstract: A design method of a shuttle mask including the following steps is provided. A first integrated circuit (IC) design is provided in a first chip region, and a second IC design is provided in a second chip region. The first IC design includes first main patterns. The second IC design includes second main patterns. First dummy insertion patterns are added in the first chip region, and second dummy insertion patterns are added in the second chip region. The first main patterns and the first dummy insertion patterns are separated from each other. The first dummy insertion patterns are patterns formed by duplicating at least one of the first main patterns. The second main patterns and the second dummy insertion patterns are separated from each other. The second dummy insertion patterns are patterns formed by duplicating at least one of the second main patterns.

Abstract: The present disclosure includes a mobile charging device and a mobile charging method. The mobile charging device includes a mobile vehicle body defining an accommodating chamber; a charging port assembly, arranged in the accommodating chamber including a mounting base and a movable base, the movable base is configured to move back and forth relative to the mounting base in a first direction; a plug assembly, including a charging plug having pins adapted to the charging interface; and a driving mechanism connected with the charging plug, and configured to drive the charging plug to move in the plug hole. The mobile vehicle body provided by the present disclosure charges external devices (electric vehicles) through a charging head.

Abstract: A networking detection method and system, relating to the technical field of electronic design automation. The method specifically comprises: an upper computer (2) allocating identifier information for each system single board (1), programmable logic array (4), and signal channel, and loading the identifier information into a corresponding controller (3) (S1); uniformly setting the signal channel to a signal receiving mode (S2); detecting whether the signal channel receives a data packet (S3); and generating one interconnection data, the upper computer (2) obtaining interconnection information according to processed interconnection data, and generating a hardware system description language file for describing networking connection (S8). By means of the processing solution, manual measurement and input are not needed, no limitation is caused by a development board installation environment, the generation speed is high, the precision is high, and a faulty cable can be accurately positioned.

Abstract: A scalable point defect qubit control system may include a diamond waveguide array comprising one or more diamond waveguides and a microwave line disposed proximally to the diamond waveguide array. Each diamond waveguide in the diamond waveguide array may include one or more qubits encoded in point defect sites. The microwave line may be configured to receive a direct current (DC) signal configured to shift an energy level of each point defect qubit of the one or more point defect qubits based on a position of the point defect in the diamond waveguide array, and receive an alternating current (AC) signal configured to control a quantum state of a point defect qubit of the one or more point defect qubits, wherein one or more properties of the AC signal are based on the shift in the energy level induced by the DC signal.

Abstract: The inventive concept provides a sensor station. The sensor station includes a body providing an inner space for storing a substrate-type sensor; a power source unit installed at the body and configured to transmit a power to the substrate-type sensor; a processing unit installed at the body and configured to process a data measured by the substrate-type sensor; and a communication unit installed at the body and configured to exchange a data with the substrate-type sensor and a server of a substrate treating system.

Abstract: An integrated circuit (IC) design layout may be partitioned into a set of content areas. A content area in the set of content areas may be divided into a set of zones based on an image-based representation of the content area. A repetition unit may be identified in a zone in the set of zones, where the repetition unit is a portion of the zone, and where the zone includes multiple instances of the repetition unit. A skeleton layout may be generated corresponding to the IC design layout, where the skeleton layout specifies locations of the multiple instances of the repetition unit in the IC design layout.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

Abstract: Embodiments include exerciser device placement in the development of an integrated circuit. Aspects of the invention include obtaining a design of an integrated circuit and creating a dynamic power blockage map for the integrated circuit. Aspects also include updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map. Based on a determination that the updated integrated circuit design complies with one or more design constraints, aspects further include outputting the updated integrated circuit design.

Abstract: Embodiments including a semiconductor device circuit for biasing gates of a qubit device as well as a method for operating the device are disclosed. The embodiments may include a multiplexed array of capacitor cells, where each capacitor cell includes a transistor-controlled capacitor, where each capacitor is connected between a drain of a respective transistor and ground, where each source of all transistors of all capacitor cells are connected to a common control point, and where each gate of the transistors of the capacitor cells are individually voltage controllable. The embodiment may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternatively activatable.

Abstract: The present disclosure relates to a computer-implemented method for automatically partitioning an electronic design. Embodiments may include accessing, using the at least one processor, the electronic design and partitioning the electronic design using a multi-mode partitioning methodology. Embodiments may further include defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies and performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

Abstract: An apparatus comprising a crystal; at least three first wires arranged substantially parallel to each other; at least two second wires arranged substantially parallel to each other, each second wire arranged non-parallel to each first wire, such that each second wire crosses each first wire, forming at least six cross points; and at least six colour centres, each colour centre located within the crystal adjacent a different one of the at least six cross points.

Abstract: The present invention discloses an inverse design method of an on-chip filter based on equivalent circuit space mapping, and belongs to the technical field of radio frequency integrated circuits. According to the present invention, based on an equivalent circuit model, a nonlinear relationship between performance parameters and structure parameters of a CMOS millimeter-wave filter is divided into two parts, namely, a part of realizing mapping from performance parameters to equivalent circuit element values by virtue of an odd and even mode theory; and a part of establishing an artificial neural network (ANN) model, in which input vectors are the equivalent circuit element values and output vectors are the structure parameters. By space mapping in the design of the present invention, the defect of discretized sampling of the scattering parameters in a traditional modeling design method is avoided; and compared with forward optimization, the required design time can be significantly shortened.

Abstract: Provided are an optical proximity correction (OPC) method capable of addressing the limitations of patterning and improving the reliability of patterning, and a mask manufacturing method using the OPC method. In the OPC method, a rectangular mask layout for a target pattern is created, the edge of the rectangular mask layout is dissected into segments, a first shape variable point is created, and a second shape variable point is created by shifting the first shape variable point on a rounded target pattern. Thereafter, a curvilinear mask layout is created based on the second shape variable point, a contour is extracted based on the curvilinear mask layout, an edge placement error (EPE) is determined, and the operations are repeated according to a predetermined criterion, thereby realizing a mask layout with minimal EPEs.

Abstract: A method of determining a quantum operation control layout for a quantum computation on a quantum system is provided. The quantum computation is to be carried out on constituents of the quantum system arranged in accordance with a mesh. Vertices of the mesh represent possible sites for the constituents of the quantum system. Each cell of the mesh indicates that quantum interactions between constituents of the quantum system arranged in that cell are possible during the quantum computation. The method includes providing a data set including data representing hyperedges of a hypergraph. The method includes determining a set of generalized cycles. The method includes determining a mesh mapping that maps data representing the hyperedges of the hypergraph or of the enlarged hypergraph to the vertices of the mesh. The method includes generating the quantum operation control layout. The quantum operation control layout includes data indicating layout vertices of the mesh.

Abstract: Systems, methods and apparatus for wireless charging are disclosed. A wireless charging device has a resonant circuit including one or more power transmitting coils in a charging surface of the charging device, a driver circuit configured to provide a charging current to the resonant circuit, and a controller. The controller is configured to determine an average transmitted power using samples of current and voltage captured from the resonant circuit, and determine that a foreign object is located on or near the charging surface when the average transmitted power exceeds a measurement of received power provided by a receiving device and parasitic losses associated with the wireless charging device. In one example, each sample of current is obtained by measuring a current flowing in the resonant circuit, and each of sample of voltage is obtained by measuring a voltage across the one or more power transmitting coils.

Abstract: A universal base for an electric toothbrush has a body comprising a top surface, a bottom surface, and a side surface therebetween. The base can be coupled with the toothbrush for wireless communication therebetween. The base includes a charging component for inductively charging the electric toothbrush, a Bluetooth component for communicating usage data received from the toothbrush during a brushing session, an analyzing component for instantaneous processing of the usage data received from the toothbrush, a timer-clock component for displaying either a count-up or a countdown of the brushing session during the brushing session and time of day before and after the brushing session, and a multi-functional light component for instantaneously communicating, during the brushing session, at least one element of the usage data.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, the apparatus includes memory, instructions, and processor circuitry to instantiate or execute the machine readable instructions to determine a design block associated with a design exception, parse the design block into a functional netlist of cell families, generate a cell occurrence counts distribution, and group cell families into cell family bins corresponding to fabrication parameters. The processor circuitry further determines inclusion of a first cell family bin does not improve one or more process technology attribute values and causes a user interface to indicate the first cell family bin as a cell family bin candidate for removal from the functional netlist.

Abstract: A method of modifying a layout for an integrated circuit (IC) includes: selecting, in the layout, a circuit region to be scaled; setting a fixed area including a fixed feature in the selected circuit region; and scaling the selected circuit region, without scaling the fixed area including the fixed feature, to obtain a modified layout for the IC.