Abstract: A method for protecting an on-board charging device includes the steps of detecting the phase and neutral voltages coming from the grid, detecting a current signal representing a compensation current generated by a compensation circuit, combining the phase voltages together so as to obtain a homopolar voltage signal, squaring the current signal and the homopolar voltage signal so as to obtain a first square current wave and a second square voltage wave, combining the first and second square waves together so as to generate an output signal having a first logic level when the first and second square waves are in phase and a second logic level when the first and second square waves are out of phase, generating a voltage increasing in proportion to the duration of each section of the output signal having the first value, comparing the voltage value with a limit value and generating an alarm signal when the voltage level exceeds the limit value.

Abstract: The present disclosure relates to a method and apparatus for generating a quantum state preparation circuit, a quantum chip, an electronic device, a storage medium, and a computer program product. The method includes: determining a target qubit set with a binary tree restriction and applying a single qubit flip gate to a first target sub-node qubit; applying a two-qubit phase offset gate between sub-node qubits; applying a two-qubit SWAP gate between the first target sub-node qubit and a second target sub-node qubit; taking the sub-node qubits as the root node qubit and iteratively performing until the sub-node qubits are leaf node qubits; and applying the two-qubit phase offset gate with a path restriction between leaf node qubits and applying a single qubit phase offset gate to the leaf node qubits to obtain a quantum state preparation circuit.

Abstract: A method for performing a computation associated with a layout of a circuit design includes, in part: generating a graph having a multitude of nodes disposed across a multitude of layers associated with the layout, wherein each node corresponds to a polygon in the layout, wherein the multitude of nodes includes a source node and a sink node; traversing from the source node to the sink node via the nodes in accordance with a rule enabling traversal between one or more of (i) nodes disposed in the same layer, and (ii) from a first node disposed in one of the layers to a node disposed in another layer that is higher than the first layer; pruning nodes that are not visited during the traversal; and maintaining nodes that are not pruned for use in the computation.

Abstract: A method of generating a circuit design parameter meeting a target specification, the method including generating a first probability distribution of a first specification using a first model provided a first parameter where the first model is configured to infer a correlation between the first parameter and the first probability distribution, generating a second parameter using a second model provided the first probability distribution, and updating the first model based on the second parameter. The second model is trained by using a reward, the reward being determined based on a second probability distribution of a second specification corresponding to the second parameter.

Abstract: An apparatus comprising: a crystal; and a colour centre located within the crystal and adapted to receive: a magnetic field, such that a projection of the magnetic field onto a colour centre axis of the colour centre causes a change in an electron spin resonance frequency of the colour centre, and an electromagnetic signal having a frequency that substantially matches the electron spin resonance frequency of the colour centre as changed by the projection of the magnetic field onto the colour centre axis.

Abstract: A charging circuit of an on-board charger, where a second end of a first power conversion circuit of the charging circuit is coupled to a first end of a second power conversion circuit, a high-voltage output end of the second power conversion circuit charges a power battery pack of an electric vehicle, and a first low-voltage output end of the second power conversion circuit supplies power to a low-voltage system of the electric vehicle. The first power conversion circuit is configured to, when the electric vehicle is in a charging mode, convert an alternating current input from a first end of the first power conversion circuit into a direct current and transmit the direct current to the first end of the second power conversion circuit.

Abstract: The present disclosure describes a system and method for determining a function for a quality of results (QoR) for a circuit design. The method includes receiving a circuit design that includes a first node, a second node, and a connection between the first node and the second node in a design space, placing an array of points within the design space, sampling first field values of the circuit design at each point of the array of points, and determining a first sampled function based on the first field values. The method includes moving the array of points within the design space, sampling second field values of the circuit design at each point of the array of points, determining a second sampled function based on the second field values, and determining a function based on the first and second sampled functions. The function produces a QoR for the circuit design.

Abstract: A design method of a shuttle mask including the following steps is provided. A first integrated circuit (IC) design is provided in a first chip region, and a second IC design is provided in a second chip region. The first IC design includes first main patterns. The second IC design includes second main patterns. First dummy insertion patterns are added in the first chip region, and second dummy insertion patterns are added in the second chip region. The first main patterns and the first dummy insertion patterns are separated from each other. The first dummy insertion patterns are patterns formed by duplicating at least one of the first main patterns. The second main patterns and the second dummy insertion patterns are separated from each other. The second dummy insertion patterns are patterns formed by duplicating at least one of the second main patterns.

Abstract: The present disclosure includes a mobile charging device and a mobile charging method. The mobile charging device includes a mobile vehicle body defining an accommodating chamber; a charging port assembly, arranged in the accommodating chamber including a mounting base and a movable base, the movable base is configured to move back and forth relative to the mounting base in a first direction; a plug assembly, including a charging plug having pins adapted to the charging interface; and a driving mechanism connected with the charging plug, and configured to drive the charging plug to move in the plug hole. The mobile vehicle body provided by the present disclosure charges external devices (electric vehicles) through a charging head.

Abstract: A networking detection method and system, relating to the technical field of electronic design automation. The method specifically comprises: an upper computer (2) allocating identifier information for each system single board (1), programmable logic array (4), and signal channel, and loading the identifier information into a corresponding controller (3) (S1); uniformly setting the signal channel to a signal receiving mode (S2); detecting whether the signal channel receives a data packet (S3); and generating one interconnection data, the upper computer (2) obtaining interconnection information according to processed interconnection data, and generating a hardware system description language file for describing networking connection (S8). By means of the processing solution, manual measurement and input are not needed, no limitation is caused by a development board installation environment, the generation speed is high, the precision is high, and a faulty cable can be accurately positioned.

Abstract: The inventive concept provides a sensor station. The sensor station includes a body providing an inner space for storing a substrate-type sensor; a power source unit installed at the body and configured to transmit a power to the substrate-type sensor; a processing unit installed at the body and configured to process a data measured by the substrate-type sensor; and a communication unit installed at the body and configured to exchange a data with the substrate-type sensor and a server of a substrate treating system.

Abstract: A scalable point defect qubit control system may include a diamond waveguide array comprising one or more diamond waveguides and a microwave line disposed proximally to the diamond waveguide array. Each diamond waveguide in the diamond waveguide array may include one or more qubits encoded in point defect sites. The microwave line may be configured to receive a direct current (DC) signal configured to shift an energy level of each point defect qubit of the one or more point defect qubits based on a position of the point defect in the diamond waveguide array, and receive an alternating current (AC) signal configured to control a quantum state of a point defect qubit of the one or more point defect qubits, wherein one or more properties of the AC signal are based on the shift in the energy level induced by the DC signal.

Abstract: An integrated circuit (IC) design layout may be partitioned into a set of content areas. A content area in the set of content areas may be divided into a set of zones based on an image-based representation of the content area. A repetition unit may be identified in a zone in the set of zones, where the repetition unit is a portion of the zone, and where the zone includes multiple instances of the repetition unit. A skeleton layout may be generated corresponding to the IC design layout, where the skeleton layout specifies locations of the multiple instances of the repetition unit in the IC design layout.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

Abstract: Embodiments include exerciser device placement in the development of an integrated circuit. Aspects of the invention include obtaining a design of an integrated circuit and creating a dynamic power blockage map for the integrated circuit. Aspects also include updating the integrated circuit design by placing one or more exercisers on the integrated circuit, wherein a location of the one or more exercisers on the integrated circuit is based on at least in part on the dynamic power blockage map. Based on a determination that the updated integrated circuit design complies with one or more design constraints, aspects further include outputting the updated integrated circuit design.

Abstract: Embodiments including a semiconductor device circuit for biasing gates of a qubit device as well as a method for operating the device are disclosed. The embodiments may include a multiplexed array of capacitor cells, where each capacitor cell includes a transistor-controlled capacitor, where each capacitor is connected between a drain of a respective transistor and ground, where each source of all transistors of all capacitor cells are connected to a common control point, and where each gate of the transistors of the capacitor cells are individually voltage controllable. The embodiment may include a charging unit connected to the common control point, and a discharging unit connected to the common control point, where the charging unit and the discharging unit are alternatively activatable.

Abstract: The present disclosure relates to a computer-implemented method for automatically partitioning an electronic design. Embodiments may include accessing, using the at least one processor, the electronic design and partitioning the electronic design using a multi-mode partitioning methodology. Embodiments may further include defining a cost function that determines a score for one or more partitioned sections of the electronic design from a plurality of partitioning methodologies and performing a routing operation on a first partitioned section and a second partitioned section from the one or more partitioned sections concurrently.

Abstract: Embodiments of the present disclosure provide enhanced systems and methods for implementing enhanced retiming of multiple clock netlists to improve integrated circuit (IC) design quality and provide enhanced retiming with reduced retiming runtime. Disclosed embodiments provide effective and efficient retiming without sacrificing netlist quality, and yield significant speedup of retiming runtime over traditional retiming.

Abstract: An apparatus comprising a crystal; at least three first wires arranged substantially parallel to each other; at least two second wires arranged substantially parallel to each other, each second wire arranged non-parallel to each first wire, such that each second wire crosses each first wire, forming at least six cross points; and at least six colour centres, each colour centre located within the crystal adjacent a different one of the at least six cross points.

Abstract: The present invention discloses an inverse design method of an on-chip filter based on equivalent circuit space mapping, and belongs to the technical field of radio frequency integrated circuits. According to the present invention, based on an equivalent circuit model, a nonlinear relationship between performance parameters and structure parameters of a CMOS millimeter-wave filter is divided into two parts, namely, a part of realizing mapping from performance parameters to equivalent circuit element values by virtue of an odd and even mode theory; and a part of establishing an artificial neural network (ANN) model, in which input vectors are the equivalent circuit element values and output vectors are the structure parameters. By space mapping in the design of the present invention, the defect of discretized sampling of the scattering parameters in a traditional modeling design method is avoided; and compared with forward optimization, the required design time can be significantly shortened.