Abstract: A semiconductor device includes a first logic gate defined within a first unit cell footprint on a semiconductor substrate. The first logic gate includes a first field effect transistor including a first gate electrode and a first source/drain region, and a second field effect transistor including a second gate electrode and a second source/drain region. A first wiring pattern is provided, which extends in a first direction across a portion of the first unit cell footprint. The first wiring pattern is electrically connected to at least one of the first gate electrode and the second source/drain region, and has: (i) a first terminal end within a perimeter of the first unit cell footprint, and (ii) a second terminal end, which extends outside the perimeter of the first unit cell footprint but is not electrically connected to any current carrying region of any semiconductor device that is located outside the perimeter of the first unit cell footprint.

Abstract: A modeling method includes the following: acquiring electrical parameters of each sub-structure in a through silicon via (TSV) structure; obtaining an electrical topology network model according to a connection relationship of each TSV structure between two dies; and obtaining a simulation model for simulation based on the electrical topology network model and the electrical parameters.

Abstract: A layout method includes: providing a library comprising a first cell and a second cell, wherein each of the first and second cells includes: a first active region and a second active region extending in a first direction; a first cell-edge gate structure and a second cell-edge gate structure extending in a second direction; and a third cell-edge gate structure and a fourth cell-edge gate structure extending in the second direction, wherein each of the first and second cell further includes one of a tie-off conductive line or a tie-off marker layer on each of the first and second cell-edge gate structures. The layout method further includes: generating a design layout by placing and abutting the first cell and the second cell; updating the design layout by performing a post-processing step on the tie-off conductive line and the tie-off marker layer of each of the first and second cells.

Abstract: A method is described. The method includes maintaining a synchronized count value in each of a plurality of logic chips within a same package. The method includes comparing the count value against a same looked for count value in each of the plurality of logic chips. The method includes each of the plurality of logic chips recording in its respective local memory at least some of its state information in response to each of the plurality of logic chips recognizing within a same cycle that the count value has reached the same looked for count value.

Abstract: Devices and methods described herein facilitate rapid wireless recharging, while reducing risk of injury, damage, or discomfort caused by heat generated during recharging. The embodiments described herein are useful in a variety of context, including for IoT devices, personal electronics, electric vehicles, and medical devices, among others. Such devices can prevent localized overheating of the device.

Abstract: A tag coordinate determination method includes: generating a tag unit for placing a detection tag; setting the detection tag and the tag unit in an image of a photomask, and obtaining a tag position file of the image, the tag position file including position coordinates of the tag unit in the image; and acquiring position coordinates of a tag to be processed in the image according to the tag position file. The tag coordinate determination method can overcome to a certain extent the problem of manually capturing the coordinates being prone to errors, thereby improving accuracy of coordinate determination.

Abstract: A quantum computing service may use multiple quantum computers to execute a same quantum computing algorithm to improve the quantum computational accuracy. The quantum computing service may instruct individual ones of the multiple quantum computers to execute the quantum computing algorithm repeatedly for a number of times. The quantum computing service may obtain a plurality of results from the multiple quantum computers. The quantum computing service may aggregate the plurality of results to generate an ensemble result, and provide the ensemble result to a customer as a final result of the quantum computing algorithm.

Abstract: A wireless power transmission system includes a wireless power transmitter, a wireless power transfer circuit electrically connectable to the at least one wireless power transmitter, and a transmitter controller. The transmitter controller is configured to perform an initial foreign object detection prior to any transmission of wireless power, the initial foreign object detection for detecting presence of a foreign object within a charge volume, the initial foreign object detection determining an initial quality factor (Q). The controller is further configured to begin wireless power transfer negotiations with one of the one or more wireless power receivers, if the initial Q has a value in a range indicating that an object in the charge volume is a wireless power receiver, and perform continuous foreign object detection, if the initial Q has the value in the range indicating that an object in the charge volume is a wireless power receiver.

Abstract: A method includes: receiving an integrated circuit design including a plurality of sub-circuits and one or more clocks to be distributed to the sub-circuits; setting one or more constraints on generating a clock network for a selected clock of the one or more clocks of the integrated circuit design; building, by a processor, a clock tree graph for the clock network for the selected clock based on a cached initial clock tree graph stored in a memory connected to the processor, the clock tree graph comprising nodes corresponding to the sub-circuits; generating a pin topology for the clock network based on the clock tree graph and the integrated circuit design; and placing, based on the pin topology, one or more pins for the clock network at one or more sides of the sub-circuits within the integrated circuit design to generate a pin placement for the clock network.

Abstract: A power conversion apparatus includes: a rotating electric machine that has a winding; an inverter that has a series-connection body of an upper arm switch and a lower arm switch; and a capacitor that is connected in parallel to the series-connection body. The power conversion apparatus includes: a connection path that, in a first storage battery and a second storage battery that are connected in series, electrically connects the winding with both a negative-electrode side of the first storage battery and a positive-electrode side of the second storage battery; and a control unit that controls switching of the upper arm switch and the lower arm switch such that a current flows between the first storage battery and the second storage battery through the inverter, the winding, and the connection path.

Abstract: A device and a method for managing batteries of a vehicle are disclosed. The device may include: batteries arranged in a vehicle, a plurality of temperature sensors mounted at different locations of the batteries, and a controller that, when a failure occurs at an arbitrary temperature sensor among the plurality of temperature sensors, estimates a temperature value at the failed temperature sensor using big data, and controls discharge of the batteries based on the estimated temperature value.

Abstract: A tensor-based computing platform performs mask synthesis. A method includes accessing a layout of a lithographic mask and estimating a printed pattern resulting from use of the lithographic mask in a lithographic process. The lithographic process is modeled by a sequence of at least two forward models. A first of the forward models uses the layout of the lithographic mask as input and a last of the forward models produces the estimated printed pattern as output. The method further includes modifying the layout of the lithographic mask based on differences between the estimated printed pattern and a target printed pattern. All of the forward models are implemented on the tensor-based computing platform.

Abstract: A system for generating a single design data file may include a processor and a memory. The processor may obtain design data including a plurality of design units. The processor may determine a first order of the plurality of design units. The processor may translate each of the plurality of design units into a corresponding file fragment by executing multiple threads of a first process. The processor may aggregate each of the plurality of file fragments into the single design data file in the first order by executing a second process in parallel to the first process.

Abstract: A power management system for use in a device comprising a battery and one or more components configured to draw electrical energy from the battery may include a first power converter configured to electrically couple between charging circuitry configured to provide electrical energy for charging the battery and the one or more downstream components and a bidirectional power converter configured to electrically couple between the charging circuitry and the battery, wherein the bidirectional power converter is configured to transfer charge from the battery or transfer charge from the battery based on a power requirement of the one or more components and a power available from the first power converter.

Abstract: An electrically excited motor drive system is integrated with an on-board charger (OBC), so that a power supply circuit that is in an electric vehicle and that is configured to drive an electrically excited motor can be integrated with an OBC of a dual active bridge (DAB) type. When a control component controls a switch circuit, the electrically excited motor drive system obtained after integration can separately implement a function of the power supply circuit or a function of the charging circuit in different working modes. In addition, when the electrically excited motor drive system is in different working modes, some circuits are further reused through time division. This addresses a problem that the power supply circuit cannot be integrated with the OBC of the DAB type, to reduce circuit complexity and costs of the electric vehicle.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

Abstract: A technique for performing lattice surgery without using twists is disclosed. Also, an error correcting code and decoder is provided that allows for error decoding of Pauli measurements performed in association with a lattice surgery operation. This allows for overall run-times of lattice surgery to be reduced. For example, some level of errors are tolerable, because they can be corrected, thus fewer measurement rounds (dm) may be performed for a given round of Pauli measurements. Additionally, a temporal encoding of lattice surgery technique is provided, which may additionally or alternatively be used to shorten run times. Also, a quantum computer layout is provided, wherein the layout includes a core computing region and a cache region. Also, protocols for swapping logical qubits between the core and cache are provided.

Abstract: A charging integrated circuit (IC) includes: a connection circuit configured to selectively connect a first battery and a second battery to each other in series and in parallel; a first charger configured to charge the first battery and the second battery connected to each other in parallel in a first charging mode; and a second charger configured to charge the first battery and the second battery connected to each other in series in a second charging mode. The connection circuit may include: a first regulating circuit connected to the first battery in series and configured to regulate a first balancing current flowing to the first battery; and a second regulating circuit connected to the second battery in series and configured to regulate a second balancing current flowing to the second battery.

Abstract: An estimation apparatus for estimating internal resistance of an engine starting battery includes a processor that executes first estimation processing for estimating the internal resistance of the battery by a first estimation method based on a current change and a voltage change of the battery at the time of cranking by an engine starting apparatus, and second estimation processing for estimating the internal resistance of the battery by a second estimation method different from the first estimation method for a period from the cranking by the engine starting apparatus to the next cranking.

Abstract: A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.