Abstract: A power control system, configured to exchange electric power with a battery pack, comprising: a power conversion device; and a controller, wherein the battery pack is configured to output a variation of a state-of-charge value among cells to the controller, the variation being determined based on at least one of a detection result from a voltage sensor or a detection result from a current sensor, and the controller is configured to control the power conversion device such that a maximum state-of-charge value among a plurality of the state-of-charge values of the cells is lower than an upper limit of a predetermined state-of-charge range and a minimum state-of-charge value among the state-of-charge values of the cells is higher than a lower limit of the predetermined state-of-charge range, the maximum state-of-charge value and the minimum state-of-charge value being values based on the variation.

Abstract: Provided are an electronic device and a control method for determining a power acquisition path at least on the basis of an attribute of power supplied from the outside of the electronic device and a state of the electronic device.

Abstract: A battery management system for a battery comprising at least one lithium sulphur battery cell. The battery management system comprising: a charging module operable to charge a lithium sulphur battery cell of the battery by delivering a pulsed charging current to the battery cell and to vary the duty cycle of the pulsed charging current so as to reduce the duty cycle of the pulsed charging current during charging of the battery cell.

Abstract: A debug system includes a chip to be tested and a debug controller. The chip to be tested includes a circuit to be tested, a debug access circuit and a debug protection circuit. When a protection function is not enabled, the debug protection circuit enables a communication between the debug access circuit and the chip to be tested, the debug controller accesses the data of the chip to be tested via the debug access circuit for debugging the circuit to be tested. When the protection function is enabled, the debug protection circuit blocks the communication between the debug access circuit and the chip to be tested, the debug controller transmits a message to the debug protection circuit via the debug access circuit, and the debug protection circuit determines whether to disable the protection function according to the message.

Abstract: A power supply system includes a set of power supply units, each power supply unit arranged electrically in series and defining a common power supply, each power supply unit having a power module and a selective bypass for selectively bypassing the respective power module. The power supply system can meet a power demand.

Abstract: Devices, systems, and methods for coupling with an implantable neurostimulator for delivering one or more electrical pulses to a target region within a patient's body are disclosed herein. A device, such as a charger, can include: a power source for storing electrical energy; a resonant circuit that can have a plurality of selectable natural frequencies; a driver coupled to the power source and the resonant circuit; and a processor coupled to the resonant circuit to control the natural frequency of the resonant circuit. The processor can determine the natural frequency of the implantable neurostimulator, and can control the resonant circuit according to the determined natural frequency of the neurostimulator.

Abstract: The present invention relates to a filter circuit (100) comprising a first and a second bulk acoustic wave resonator (2, 3), the first resonator (2) having a first piezoelectric layer (4) structured such that the first resonator (2) has a lower resonant frequency than the second resonator (3), wherein the first piezoelectric layer (4) is structured by recesses (14) passing through the first piezoelectric layer (4), the first resonator (2) and the second resonator (3) as series resonators (102, 105) connected in series with a signal path of the filter circuit (100) or wherein the first resonator (2) and the second resonator (3) as parallel resonators (103, 106) are connected to the signal path of the filter circuit (100) in such a way that in each case one electrode of the resonators is connected to the signal path.

Abstract: Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

Abstract: Systems and methods for luggage systems are provided. The luggage systems and methods include a luggage housing assembly having a front housing portion and a rear housing portion connected to the front housing portion by a hinge. The luggage systems and methods include a set of wheels mounted to the luggage housing assembly. The luggage systems and methods can include a rechargeable power supply assembly that includes a housing component and a battery module casing configured to receive a rechargeable battery module. The luggage systems and methods can include a compression pad subsystem configured to compress contents of the luggage within the housing portions.

Abstract: A wireless temperature-measurement system comprising (a) one or more temperature probes each including one or more energy-storage capacitors which supply the electrical energy for operation of the probe(s) and (b) a probe-charging station having circuitry configured to supply electric charge to the energy-storage capacitors prior to the temperature probes being positioned to measure temperature.

Abstract: Described are various embodiments of a system and method for verifying extracted integrated circuit (IC) features representative of a source IC and stored in a feature dataset structure. Generally, a set of extracted IC features imaged within a designated IC area is converted into a static tile image. The static tile image is then rendered for visualization as an interactive mapping of the feature dataset structure within the area. Corrections for one or more of the set of extracted IC features are received based on the static tile image and input corrections are executed on the feature dataset structure to produce an updated feature dataset structure.

Abstract: A power storage system with excellent characteristics is provided. A power storage system with a high degree of safety is provided. A power storage system with less deterioration is provided. A storage battery with excellent characteristics is provided. The power storage system includes a neural network and a storage battery. The neural network includes an input layer, an output layer, and one or more hidden layers between the input layer and the output layer. The predetermined hidden layer is connected to the previous hidden layer or the previous input layer by a predetermined weight coefficient, and connected to the next hidden layer or the next output layer by a predetermined weight coefficient. In the storage battery, voltage and time at which the voltage is obtained are measured as one of sets of data. The sets of data measured at different times are input to the input layer and the operational condition of the storage battery is changed in accordance with a signal output from the output layer.

Abstract: A battery charging circuit can include: a primary rectifier circuit configured to rectify an input AC voltage into a rectified voltage signal; a DC-DC converter configured to generate a charging current according to the rectified voltage signal, in order to charge a battery; a control circuit configured to adjust the charging current by controlling an operation state of the DC-DC converter according to a charging requirement, in order to make an average value of the charging current meet the charging requirement; and where the charging current is controlled to be zero when an absolute value of the input AC voltage is lower than a predetermined threshold.

Abstract: A method (of manufacturing a semiconductor device) includes: forming active regions including spacing apart neighboring active regions resulting in corresponding gaps; forming gate structures (overlying the active regions and the gaps) including locating intra-gap segments of the gate structures over the gaps, arranging each intra-gap segment to include two end regions separated by a central region, and at intersections between active regions and gate structures that is designated to be non-functional (flyover intersection), preventing formation of a functional connection between the two; and removing selected portions of at least some of the intra-gap segments including removing central regions of first selected intra-gap segments substantially without removing portions of corresponding end regions of the first selected intra-gap segments, and removing central regions and portions of end regions of second selected intra-gap segments for which corresponding end regions of the second intra-gap segments abut fl

Abstract: A method for obtaining learned self-consistent electron density and/or derived physical quantities includes: conducting non-self-consistent (NSC) calculation to generate a first NSC dataset X1 from a first plurality of configurations of atoms; conducting self-consistent (SC) calculation to generate a first SC dataset Y1 from the first plurality of configurations of atoms; mapping the first NSC dataset X1 to the first SC dataset Y1 utilizing machine learning algorithm to generate a mapping function F; and generating a learned self-consistent data Y2 from a new NSC data X2 utilizing the mapping function F.

Abstract: A management device 50 for power storage elements is provided with a cause analysis unit 51 that, when the voltages of power storage elements B1-B4 are reduced to a prescribed level or physical quantities correlated with the voltages are reduced to prescribed values after the supply of power to the power storage elements B1-B4 has been stopped, analyzes the cause of the voltage reduction in power storage elements B1-B4 or the cause of the reduction in the physical quantities correlated with voltages to the prescribed values, on the basis of measurement data of the power storage elements B1-B4 measured after the supply of power has been stopped.

Abstract: The disclosure describes the implementation of automated techniques for optimizing quantum circuits of the size and type expected in quantum computations that outperform classical computers. The disclosure shows how to handle continuous gate parameters and report a collection of fast algorithms capable of optimizing large-scale-scale quantum circuits. For the suite of benchmarks considered, the techniques described obtain substantial reductions in gate counts. In particular, the techniques in this disclosure provide better optimization in significantly less time than previous approaches, while making minimal structural changes so as to preserve the basic layout of the underlying quantum algorithms.

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

Abstract: A method includes: accessing a design data of an integrated circuit (IC), wherein the design data includes a transistor layer and a plurality of metal layers over the transistor layer; assigning a bin size for each of the metal layers based on layout properties of the respective metal layers, wherein a bin size of a higher larger of the metal layers has a greater bin size than that of a lower layer of the metal layers; performing resource planning on the transistor layer and each of the metal layers according to the assigned bin sizes of the respective metal layers; and updating the design data according to the resource planning. At least one of the accessing, assigning, performing and updating steps is conducted by at least one processor.

Abstract: A method for battery charging includes performing a first-constant-current charging the battery with a constant current having a first intensity, determining a voltage of the battery rises above a first voltage level, performing a second-constant-current charging of the battery with a constant current having a second intensity that is less than the first intensity, determining a voltage of the battery rises above a second voltage level that is higher than the first voltage level, performing a third-constant-current charging the battery with a constant current having a third intensity that is less than the second intensity, determining a voltage of the battery rises above a third voltage level that is higher than the second voltage level, performing a constant voltage charging the battery with a constant voltage having the third voltage level, determining a charging current of the battery falls to a fourth intensity that is less than the third intensity.