Abstract: An adaptive logical storage element comprises a plurality of solid-state storage elements accessible in parallel. The logical storage element includes logical storage units, which may include logical page, logical storage divisions (erase blocks), and so on. Each logical storage unit comprises a plurality of physical storage units. A logical storage unit may include one or more physical storage units that are out-of-service (OOS). The OOS status of logical storage units is tracked by OOS metadata. When data is stored on the logical storage element, padding data is provided to physical storage units that are OOS, and valid and/or parity data is provided to in-service physical storage units. A write data pipeline accesses the OOS metadata to insert padding data, and a read data pipeline accesses the OOS metadata to strip padding data.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, a memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit. A controller circuit communicates a first command to the MME circuit to perform a selected action upon a selected address of the NVM. After a variable delay time interval, a second command is communicated by the controller circuit to the MME circuit as a status request regarding the first command. The variable delay time interval is determined based on an accumulated count of status requests that were issued, prior to the first command, for the selected address.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Abstract: A cache device of an embodiment includes a tag/data memory. The tag/data memory includes a storage area capable of storing a plurality of pieces of tag data and a plurality of pieces of compressed cache data corresponding to the plurality of pieces of tag data; and each of the pieces of tag data includes a flag indicating whether the piece of tag data is a piece of tag data read last or not and a compression information field C indicating whether each of the pieces of cache data is compressed or not.

Abstract: Embodiments of the present disclosure provide a method and apparatus for dynamic storage tiering by calculating a density of data according to a temperature of the data, and making the density of data with a higher temperature smaller; obtaining density threshold of each of the tiers, wherein the density threshold of an upper tier is smaller than that of a lower tier; comparing the density of the data with the density threshold of each of the tiers to determine which tier the data should be moved to; and moving the data to the determined tier. Embodiments of the present invention may be used to provide a dynamic storage tiering scheme with higher flexibility and scalability.

Abstract: A technique for storing data operates a replication splitter in a host computing device. The host computing device runs an application and monitors write performance from the application to both a data storage array and a replication site. If the monitored performance indicates that writes to the replication site would not significantly slow down the application, the replication splitter operates in synchronous mode, in which the splitter waits to acknowledge writes from the application until it receives confirmation of write completion from both the data storage array and the replication site. However, if the monitored performance indicates that writes to the replication site would significantly slow down the application, the replication splitter operates in asynchronous mode, in which the splitter acknowledges writes from the application as soon as it receives confirmation that the data storage array has completed those writes and without waiting for acknowledgements from the replication site.

Abstract: A storage device includes one or more nonvolatile memories, and a memory controller that controls the nonvolatile memories such that write data of data streams is stored in the nonvolatile memories. The data streams have a first number of requested stream identifiers provided from a host. The memory controller includes a write amount manager that manages information about a data amount of each of the data streams having the requested stream identifiers, a stream manager that maps the first number of the requested stream identifiers with a second number of processing stream identifiers, depending on the information associated with the data amount, such that the data streams are provided to the nonvolatile memories according to the second number of processing stream identifiers, and a mapping manager that manages information about mapping between the first number of the requested stream identifiers and the second number of the processing stream identifiers.

Abstract: An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory devices. The memory card is configurable to implement a first portion of the storage space of the non volatile memory devices as system memory. The memory card also includes a controller to manage, upon a power down event, the transfer of information from the volatile memory devices into a second portion of the storage space of the non volatile memory devices.

Abstract: Embodiments of systems, method, and apparatuses for remote monitoring are described. In some embodiments, an apparatus includes at least one monitoring circuit to monitor for memory accesses to an address space; at least one a monitoring table to store an identifier of the address space; and a tag directory per core used by the core to track entities that have access to the address space.

Abstract: Methods and apparatuses to control access to a multiple bank data cache are described. In one embodiment, a processor includes conflict resolution logic to detect multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle and to grant access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache. In another embodiment, a method includes detecting multiple instructions scheduled to access a same bank of a multiple bank data cache in a same clock cycle, and granting access priority to an instruction of the multiple instructions scheduled to access a highest total of banks of the multiple bank data cache.

Abstract: The present disclosure relates to memory array access control. An apparatus includes partition control circuitry to control at least one partition of a memory array, the at least one partition control circuitry also to receive a controlled clock signal to enable execution of a legitimate memory access command and to generate an active/idle signal having an active state when executing the legitimate memory access command and an idle state when executing the legitimate memory access command is complete; wherein the clock signal is disabled when the active/idle signal is in an idle state.

Abstract: A storage device includes a memory device configured to store data and a memory controller connected to the memory device through a data strobe line and a plurality of data lines. The storage device adds a predetermined specific pattern in front of data and processes data input following the specific pattern as valid data during a read or write operation. The specific pattern is provided in alignment with a data strobe signal (DQS) latency cycle. The memory controller detects a specific pattern input from the memory device during a read operation and processes data input following the specific pattern as valid data when the detected specific pattern matches an internally stored specific pattern.

Abstract: Techniques are disclosed for drive zeroing that create and maintain a memory resident zeroing map for each drive in a data storage system. The disclosed techniques create, for each drive in an array of non-volatile data storage devices, a zeroing map. The zeroing map for a drive includes multiple slots, each of which corresponds to a data storage area of the drive. Each slot in the zeroing map for a drive stores a zeroing status of the corresponding data storage area. The value of a slot in the zeroing map may indicate that the zeroing status of the corresponding data storage area is i) zeroed, indicating that the corresponding data storage area has previously been zeroed, or ii) unknown, indicating that the zeroing status of the corresponding data is unknown, i.e. the corresponding data storage area may or may not have previously been zeroed.

Abstract: Provided are a computer program product, system and method for managing read/write operations in a hybrid memory device system. Determinations are made of an available physical address in a first memory device for a data block to allocate for metadata for a file or directory in a file system and a first logical address corresponding to the available physical address in a first range of logical addresses. Determinations are made of an available physical address in a second memory device for a data block to allocate for the file or directory in the file system and a second logical address corresponding to the available physical address in the second memory device in a second range of logical addresses. The second logical address is used to access the data block allocated to the file or directory in the file system.

Abstract: According to an embodiment, an update request reception unit receives a data update request to update data stored in a storage. A read request unit makes a read request to read data from the storage. A data reception unit receives the data from the storage. An update value calculator calculates an update value of the received data. A write request unit makes a write request to write the calculated update value into the storage. A data processing execution unit executes reading and writing on the storage. A history processing unit generates a history of the reading and deletes a history of reading corresponding to the writing. An update information estimator estimates, from the generated history, update information indicating how the data is to be updated. A data update unit updates the data read according to the estimated update information and output new updated data to the data reception unit.

Abstract: A system and method for improving the management of data input and output (I/O) operations for Shingled Magnetic Recording (SMR) devices in a network storage system is disclosed. The storage system includes a storage controller that receives a series of write requests for data blocks to be written to non-sequential addresses within a pool of SMR devices. The storage controller writes the data blocks from the series of write requests to a corresponding sequence of data clusters allocated within a first data cache of the storage controller for a thinly provisioned volume of the pool of SMR devices. Upon determining that a current utilization of the first data cache's data storage capacity exceeds a threshold, the sequence of data clusters including the data blocks from the first data cache are transferred to sequential physical addresses within the SMR devices.

Abstract: A multi-mode hybrid memory drive comprises a bulk memory device and a removable cache memory device. A controller of the bulk memory device may be configured to operate the bulk memory device in either a stand-alone mode or a hybrid mode responsive to detecting the removable cache memory device being coupled with a cache port of the bulk memory device. A method of operating a multi-mode hybrid drive may also comprise monitoring a cache port of a bulk memory device to determine a presence of a removable cache memory device, operating the bulk memory device as a stand-alone drive responsive to determining the removable cache memory device is not present, and operating the bulk memory device as a hybrid drive using the removable cache memory device as a data cache responsive to determining the removable cache memory device is present. Additional hybrid memory drives and computer systems are also described.

Abstract: Systems and methods for tracking memory allocation within shared memory are provided. In one embodiment, a method includes tracking memory allocation within shared memory. The method includes receiving instructions to execute a process. The method includes assigning a process identifier to the process. The method includes allocating one or more blocks of the shared memory to store process specific data associated with the process, wherein the one or more blocks of the shared memory are addressable with a reference. The method includes storing the process identifier at an index in a first array. The method includes storing, by the one or more processors, the reference to the one or more blocks of the shared memory at the index in a second array.

Abstract: A computing system includes: an instruction dispatch module module configured to receive a program instruction; and an address reordering module, coupled to the instruction dispatch module, configured to filter the program instruction when the program instruction is a hit in a cache-line in a prefetch filter. The computer system further includes: an instruction dispatch module configured to receive a program instruction; an address reordering module, coupled to the instruction dispatch module, configured to: allocate a tag in a tag module for the program instruction in a program order, allocate a virtual address in a virtual address module for the program instruction and out-of-order relative to the program order, and insert a pointer associated with the tag to link the tag to the virtual address.

Abstract: In one embodiment, a computer program product is configured for performing deduplication in conjunction with random read and write operations across a namespace divided into a plurality of disjoint regions. The computer program product includes a computer readable storage medium having program instructions embodied therewith, where the computer readable storage medium is not a transitory signal per se. The program instructions are executable by a computer to cause the computer to perform a method including: maintaining a metadata structure for each of the plurality of disjoint regions via the respective region manager(s) of the plurality of disjoint regions, each metadata structure comprising metadata indicating a physical storage location of one or more data chunks associated with the respective region; and performing, by the computer, a deduplicated write operation of a first data chunk in a first region of the plurality of disjoint regions.