Abstract: According to one embodiment, a storage system includes a first storage and a controller which controls the first storage. The first storage includes a first group which includes a plurality of pages which are data write units and include first nonvolatile memories, and a first counter which counts the number of data writes to the first group. The controller determines whether all the pages in the first group has been written to or not.

Abstract: A policy-based orchestration method in an exascale class cloud storage environment, and a storage system using the same are provided. The storage orchestration method includes: allocating a combination of different storages to a user as a storage space; and adjusting the combination according to a user's using pattern. Accordingly, the storage can be operated optimally and autonomically, and thus can be operated efficiently and economically.

Abstract: Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each of a plurality of threads are assigned to one of a plurality of segments in a buffer, wherein the threads write to the segment to which they are assigned. A free segment list indicates segments which are not assigned to one of the threads. In response to one of the segments assigned to one of the threads becoming a full segment having less than a threshold amount of free space, indicating the full segment assigned to the thread in the free segment list and assigning one of the segments in the free segment list to the thread different from the full segment.

Abstract: A computing system includes a memory storage unit, having memory blocks, configured as a memory cache to store values of key-value pairs; and a device control unit, coupled to the memory storage unit, configured to: identify eviction targets from key-value eviction candidates in a key-value registry based on an eviction policy; calculate an associated eviction count of associated eviction candidates within the same instance of the memory blocks as the eviction targets; select an erase block as the memory blocks associated with the highest value of the associated eviction count; and interface with the memory storage unit to perform an erase operation on the erase block.

Abstract: An approach for using a storage library to translate commands from one command language into a different command language. The approach includes receiving a storage request in a command language from an application. The storage request is directed to a target storage device that uses a different command language. The storage request is translated into the different command language of the target storage device using a storage library of command languages and the storage request is performed.

Abstract: An apparatus includes a storage resource to store data. The data can be accessible by a host computer system. The apparatus includes a set of dynamically powered volatile memory devices that are configured to store mapping information. The mapping information maps logical addresses of received access requests to corresponding physical addresses of the storage resource to which the access requests pertain. In accordance with received mode setting information, the controller logic adaptively controls power settings of the volatile memory devices storing the mapping information. If an abundance of power such as 120 VAC power is available, more of volatile memory devices can be powered to store a greater portion of the mapping information. If only battery power is available, fewer than all of the volatile memory devices can be powered to store a smaller portion of the mapping information.

Abstract: A device includes, a memory, and, a processor coupled to the memory, including a cache memory, and configured, to hold a memory access instruction for executing an access to the memory and a prefetch instruction for executing a prefetch to the memory, to determine whether or not data which is a subject data of the memory access instruction is held in the cache memory, and when the data is held in the cache memory and when a corresponding prefetch instruction that is a prefetch instruction corresponding to the memory access instruction is held in the processor, not to execute an execution of the corresponding prefetch instruction.

Abstract: An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.

Abstract: A controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that include multiple memory blocks. The processor is configured to hold information regarding power consumption of the memory blocks, to group at least some of the memory blocks into one or more storage groups, based on the information, such that the memory blocks in each storage group jointly consume less than a predefined power limit when the memory blocks in the storage group are applied a storage operation in parallel, and to apply the storage operation, in parallel, to the memory blocks in a selected storage group.

Abstract: According to one configuration, a memory system includes a configuration manager and multiple memory devices. The configuration manager includes status detection logic, retrieval logic, and configuration management logic. The status detection logic receives notification of a failed attempt by a first memory device to be initialized with custom configuration settings stored in the first memory device. In response to the notification, the retrieval logic retrieves a backup copy of configuration settings information from a second memory device in the memory system. The configuration management logic utilizes the backup copy of the configuration settings information retrieved from the second memory device to initialize the first memory device.

Abstract: A method, computer program product, and computing system for identifying a data portion having temporally-variable utilization. A utilization schedule is defined for the data portion, wherein the utilization schedule defines at least one high-utilization temporal period and at least one low-utilization temporal period. The data portion is accessed through a higher-performance storage system during the high-utilization temporal period. The data portion is accessed through a lower-performance storage system during the low-utilization temporal period.

Abstract: A processor in described having an interface to non-volatile random access memory and logic circuitry. The logic circuitry is to identify cache lines modified by a transaction which views the non-volatile random access memory as the transaction's persistence storage. The logic circuitry is also to identify cache lines modified by a software process other than a transaction that also views said non-volatile random access memory as persistence storage.

Abstract: Non-volatile devices may be configured such that a clear operation on a single bit clears an entire block of bits. The representation of particular data structures may be optimized to reduce the number of clear operations required to store the representation in non-volatile memory. A data schema may indicate that a data structure of an application may be optimized for storage in non-volatile memory. A translation layer may convert an application level representation of a data value associated with the data structure to an optimized storage representation of the data value before storing the optimized storage representation of the data value in non-volatile memory.

Abstract: Systems and methods for enabling programmable cache size via Class of Service (COS) cache allocation are described. In some embodiments, a method may include: identifying a resource available to an Information Handling System (IHS) having a cache, where the resource is insufficient to allow the entire cache to be flushed during a power outage event; dividing a cache into at least a first portion and a second portion using a COS cache allocation, where the second portion has a size that is entirely flushable with the resource; and flushing the second portion of the cache during the power outage event.

Abstract: Semiconductor storage devices and methods of operating the same are provided. The semiconductor storage device including a non-volatile memory device, and a memory controller configured to control the non-volatile memory device, the memory controller including a performance control module, the performance control module configured to control a performance level of the memory controller based on state information of the memory controller may be provided.

Abstract: A data storage network is provided. The network includes a client connected to the data storage network; a plurality nodes on the data storage network, wherein each data node has two or more RAID controllers, wherein a first RAID controller of a first node is configured to receive a data storage request from the client and to generate RAID parity data on a data set received from the client, and to store all of the generated RAID parity data on a single node of the plurality of nodes.

Abstract: Implementations of the present disclosure include methods, systems, and computer-readable storage mediums for identifying a data processing function to be executed in a hybrid main memory system, the hybrid main memory system including a first type of main memory and a second type of main memory, the data processing function including data access operations to access the hybrid main memory system, accessing a write metric for the data processing function, the write metric based at least in part on a proportion of the data access operations that are write operations, and, based at least in part on the write metric being less than a threshold value, designating the data processing function for execution in the first type of main memory.

Abstract: A semiconductor system may include a plurality of memory devices corresponding to a plurality of channels, an address mapping unit suitable for converting addresses corresponding to provided external requests according to a selected address map among a plurality of address maps; a monitoring unit suitable for monitoring the external requests provided to each of the plurality of channels, and a control unit suitable for providing a control signal for controlling the address mapping unit to select an address map according to a result of the monitoring.

Abstract: Technologies are generally described for systems, devices and methods effective to accelerate memory access. A memory unit, including a memory and a programmable circuit, may be in communication with a processor executing a virtual machine. The memory unit may receive from the processor, a request to configure the programmable circuit in accordance with a program. The program may be associated with the virtual machine. The programmable circuit may be configured in accordance with the program. The programmable circuit may then be operated to perform one or more operations on data in the memory.

Abstract: Methods and systems for normalizing a read-write cache allocation pool for virtual desktop infrastructure (VDI) workloads are disclosed. The method includes determining a cache allocation policy; determining a range of expected input/output (I/O) levels of a storage system; determining a current I/O level of the storage system; determining a target cache allocation based on the cache allocation policy, the range of expected I/O levels, and the current I/O level, the target cache allocation including a first memory region allocated to read cache operations and a second memory region allocated to write cache operations; and reallocating cache memory based on the target cache allocation.