Patents Examined by Brian R. Peugh
  • Patent number: 12141072
    Abstract: Techniques described herein relate to a method for managing training data. The method includes monitoring, by a training data stream manager (TDSM), a cache comprising a plurality of training data examples associated with streams of mini-batch sequences scheduled to be transmitted to a machine learning training environment; making a first determination that a cache eviction is required; in response to the first determination: selecting a training data example of the plurality of training data examples; making a second determination that the training data example is eligible for cache eviction; in response to the second determination: evicting the training data example from the cache; and updating a training data example database entry to indicate that the training data example is evicted from the cache.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: November 12, 2024
    Assignee: Dell Products, L.P.
    Inventors: John Thomas Cardente, Qi Bao
  • Patent number: 12131072
    Abstract: Various implementations described herein relate to systems and methods for enabling a data lane for communicating messages for each of a plurality of regions of a non-volatile memory. Each of the plurality of regions includes a plurality of dies. The messages for each of the plurality of regions are communicated via the data lane.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: October 29, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Amit Rajesh Jain
  • Patent number: 12131061
    Abstract: Memory systems and operating methods of the memory systems are disclosed. In an implementation, a memory system includes a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas, and a buffer manager configured to designate an address of a buffer area in which a defect occurs as a defect address by comparing a first parity bit for data stored in the system buffer with a second parity bit that is obtained by a computation based on the data stored in the system buffer, and block access to the buffer area designated as the defect address.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: October 29, 2024
    Assignee: SK HYNIX INC.
    Inventor: In Jong Jang
  • Patent number: 12124707
    Abstract: A memory controller of a memory system classifies input and output commands issued by a host into a group of read commands and a group of write commands, and manages the group of read commands and the group of write commands using first and second queues, respectively. The controller continuously processes a first group of commands among the group of read commands and the group of write commands until a first time period has elapsed from a start of the continuous processing of the first group of commands. In response to the first time period having elapsed, the controller switches a process target from the first group of commands to a second group of commands that is different from the first group of commands and selected among the group of read commands and the group of write commands.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: October 22, 2024
    Assignee: Kioxia Corporation
    Inventors: Konosuke Watanabe, Hajime Yamazaki
  • Patent number: 12099735
    Abstract: A memory system includes a memory controller configured to write data in a first mode to a first block of a first area of a non-volatile memory. The first mode is a write mode for writing data with a first number of bits per memory cell. The memory controller is further configured to execute copy processing on the data written in the first mode to the first block, by writing system data written in the first block to a second block of the first area in the first mode and writing user data written in the first block to a third block of a second area of the non-volatile memory in the second mode. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: September 24, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomoyuki Kantani, Kousuke Fujita, Iku Endo
  • Patent number: 12093574
    Abstract: Disclosed herein are an apparatus and method for managing memory-based integrated storage. The apparatus includes one or more processors and executable memory for storing at least one program executed by the one or more processors. The at least one program converts data operation tasks in response to a request for access to memory-based integrated storage from a user, a single virtual disk of a virtual storage pool of the memory-based integrated storage converts a disk access command into a command for connecting to a storage backend depending on the data operation tasks, and conversion of the data operation tasks into the command includes target identification indicating which local storage of the memory-based integrated storage is to be used.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: September 17, 2024
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Dae-Won Kim, Sun-Wook Kim, Su-Min Jang, Jae-Geun Cha, Hyun-Hwa Choi
  • Patent number: 12086423
    Abstract: An operation method of memory may include activating a first row that is selected in a first bank, activating a second row that is selected in a second bank, receiving an all-bank counting command, reading a first access count from memory cells of specific columns of the first row in response to the all-bank counting command, increasing the first access count, writing the increased first access count in the memory cells of the specific columns of the first row, reading a second access count from memory cells of specific columns of the second row in response to the all-bank counting command, increasing the second access count, and writing the increased second access count in the memory cells of the specific columns of the second row.
    Type: Grant
    Filed: July 6, 2023
    Date of Patent: September 10, 2024
    Assignee: SK hynix Inc.
    Inventor: Jeong Jun Lee
  • Patent number: 12079519
    Abstract: Techniques are provided for implementing a distributed control plane to facilitate communication between a container orchestration platform and a distributed storage architecture. The distributed storage architecture hosts worker nodes that manage distributed storage that can be made accessible to applications within the container orchestration platform through the distributed control plane. The distributed control plane includes control plane controllers that are each paired with a single worker node of the distributed storage architecture. The distributed control plane is configured to selectively route commands to control plane controllers that are paired with worker nodes that are current owners of objects targeted by the commands. If ownership of an object has changed from one worker node to another worker node, then subsequent commands will be re-routed to a control plane controller paired with the other worker node now owning the object.
    Type: Grant
    Filed: October 16, 2023
    Date of Patent: September 3, 2024
    Assignee: NetApp, Inc.
    Inventors: Praveen Kumar Hasti, Christopher Alan Busick
  • Patent number: 12079497
    Abstract: To quickly and appropriately adjust a performance of a storage system. A storage configuration optimization device for managing a storage system including one or more storages implemented by a plurality of SDS nodes includes a virtual CPU. The virtual CPU is configured to receive a request for an execution period and a necessary performance of a project using the storage system, and select, based on consumption information and performance information of a resource of the storage system, one or more change patterns satisfying the request for the execution period and the necessary performance from among a plurality of change patterns indicating configuration changes of the storage system.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: September 3, 2024
    Assignee: HITACHI, LTD.
    Inventors: Miho Kobayashi, Akira Deguchi, Kazuki Togo, Tsukasa Shibayama, Takanobu Suzuki
  • Patent number: 12067274
    Abstract: A method is provided. The method includes receiving a set of data blocks to be stored in a storage system. The storage system includes a plurality of non-volatile memory modules. The method also includes generating a set of segments based on the set of data blocks. A respective segment comprising portions of one or more erase blocks. The method further includes writing the set of segments to the non-volatile memory modules based on orderings of the portions of the one or more erase blocks.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: August 20, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Benjamin Scholbrock, Andrew R. Bernat, Ronald Karr, Xiaohui Wang
  • Patent number: 12061525
    Abstract: Techniques are provided for a snapshot difference interface integrated into an object store data management container. The snapshot difference interface is capable of interpreting an object format and snapshot file system format of snapshots backed up to an object store within objects formatted according to the object format. The snapshot difference interface can identify differences between snapshots, such as files that changed between the snapshots, while the snapshots are still resident within the object store. Because the snapshot difference interface does not retrieve the snapshots from the object store, security is improved, resource and network consumption is reduced, there is less of an impact upon client I/O processing, and a catalog of the snapshots can be more efficiently built and recovered in the event of corruption.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: August 13, 2024
    Assignee: NetApp, Inc.
    Inventors: Tijin George, Sharankumar Yelheri
  • Patent number: 12056396
    Abstract: An illustrative method includes a storage-aware serverless function management system receiving a request to execute a serverless function instance of a serverless function implemented in a serverless system, the serverless function instance associated with a component of a storage system, determining a portion of the component accessible to the serverless function instance based on a storage system policy associated with the storage system, and executing the serverless function instance using the portion of the component of the storage system.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: August 6, 2024
    Assignee: Pure Storage, Inc.
    Inventors: Taher Vohra, Luis Pablo Pabón
  • Patent number: 12056362
    Abstract: Various implementations relate to receiving, by a non-volatile memory device from a host, a host command include device context information of non-volatile memory devices. The device context includes an address of a buffer of each non-volatile memory device. In response to receiving the host command, portions of host data are divided among the non-volatile memory devices. The non-volatile memory device sends to the host a transfer request indicating transfer of each portion of the host data to a respective one of the non-volatile memory devices. The non-volatile memory device sends to another non-volatile memory device a peer command based on the device context information.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: August 6, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Mohinder Saluja
  • Patent number: 12050799
    Abstract: A first compute server of a distributed cloud computing network executes an application that controls reading and writing access to associated persistent data. The first compute server performs a write operation to the persistent data on local storage, notifies a piece of code that controls outgoing messages from the application that the write operation is pending, and transmits write information for the write operation to a set of other compute servers. If an acknowledgement of the write information is received from a quorum of the other compute servers, the application notifies the piece of code that the write operation is confirmed. Periodically the write information is transmitted to an external storage system. If a confirmation that the write information has been written is received from the storage system, the first compute server transmits a write confirmation notice to the other compute servers, which can then delete the write information.
    Type: Grant
    Filed: December 29, 2023
    Date of Patent: July 30, 2024
    Assignee: CLOUDFLARE, INC.
    Inventors: Kenton Taylor Varda, Glen Patrick Maddern, Alex Dwane Robinson
  • Patent number: 12050797
    Abstract: An object of the invention is to optimize a storage cost for data. There is provided a storage system including a storage device, a memory, and a processor configured to control input and output of data to and from the storage device. The processor monitors a storage amount that is at least one of a write amount (a total amount of data received as a write target) and a physical use amount (a total amount of data physically stored in the storage device), and a read amount (a total amount of data that is read), and calculates a fee as a storage cost that is a cost related to use of the storage device in a target period, based on a storage amount and a read amount in the target period in accordance with a monitoring result.
    Type: Grant
    Filed: August 1, 2022
    Date of Patent: July 30, 2024
    Assignee: HITACHI, LTD.
    Inventors: Hiroaki Akutsu, Takahiro Naruko, Akifumi Suzuki
  • Patent number: 12050530
    Abstract: A method for performing table management of a memory device in predetermined communications architecture with aid of system-region garbage collection (GC) and associated apparatus are provided. The method may include: utilizing the memory controller to perform a system-region GC procedure to manage at least one table regarding internal management of the memory device. The system-region GC procedure may include: reading a set of first table contents from a set of first table pages; and writing the set of first table contents into a set of first system-region-GC-processed table pages of the at least one table block, and writing a first RAID parity of the set of first table contents into a first parity page corresponding to the set of first system-region-GC-processed table pages in the at least one table block, in order to generate a first system-region-GC-processed table RAID protection group, for protecting the set of first system-region-GC-processed table pages.
    Type: Grant
    Filed: March 23, 2023
    Date of Patent: July 30, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Jie-Hao Lee, Chen-Yin Lin, Chih-Wei Hsiao
  • Patent number: 12050779
    Abstract: The present disclosure includes apparatuses, methods, and systems for storing non-volatile memory initialization failures. In an example, a method can include initializing a volatile memory die, initializing a first non-volatile memory die in response to initializing the volatile memory die, copying executable instructions from the first non-volatile memory die to the volatile memory die in response to initializing the first non-volatile memory die, initializing the second non-volatile memory die in response to initializing the first non-volatile memory die, and storing a failure record in the first non-volatile memory die in response to an error occurring during the initialization of the second non-volatile memory die.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: July 30, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Qi Dong
  • Patent number: 12038848
    Abstract: This application is directed to compressing a logical-to-physical (L2P) address indirection table in a memory system of an electronic device. The electronic device determines a plurality of physical addresses corresponding to an ordered sequence of logical addresses. Each logical address corresponds to a distinct physical address. The electronic device identifies a set of most significant bits (MSBs) and a set of least significant bits (LSBs) of each of the plurality of physical addresses and determines a set of data bits based on a plurality of MSB sets including the set of MSBs of each of the plurality of physical addresses. The set of LSBs of each of the plurality of physical addresses and the set of data bits are stored jointly in the L2P address indirection table.
    Type: Grant
    Filed: March 28, 2023
    Date of Patent: July 16, 2024
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventor: Zion Kwok
  • Patent number: 12026385
    Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: July 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Jiangang Wu, Jung Sheng Hoei, Qisong Lin, Kishore Kumar Muchherla
  • Patent number: 12019545
    Abstract: A memory system includes: a main memory device configured to include a plurality of row lines; a cache memory device configured to include a plurality of cache lines for caching data stored in the row lines, each cache line including cache data, a row hammer state value for storing an access number of a corresponding row line, and an access selection bit set according to the row hammer state value; and a memory controller configured to control an access operation to be performed on one of the main memory device and the cache memory device, which is selected according to the access selection bit of a cache-hit cache line, in response to a request from a host.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: June 25, 2024
    Assignee: SK HYNIX INC.
    Inventors: Sung Woo Hyun, Myoung Seo Kim, Jae Hoon Kim