Abstract: Provided is a method for manufacturing a semiconductor device, the semiconductor device including a substrate, and an oxide semiconductor TFT that is supported by the substrate and includes an oxide semiconductor film as an active layer. The method includes: (A) preparing MO gas containing a first organometallic compound that contains In and a second organometallic compound that contains Zn; and (B) supplying gas containing the MO gas and oxygen to the substrate placed in a chamber under a condition in which the substrate is heated to 500° C. or lower, and growing an oxide semiconductor film containing In and Zn on the substrate using an MOCVD method. Step (B) is performed under a condition in which plasma is formed in the chamber.

Abstract: A method for inline inspection during semiconductor wafer fabrication is provided. The method includes forming a plurality of test structures on a semiconductor wafer along two opposite directions. An offset distance between a sample feature and a target feature of each of the test structures increases gradually along the two opposite directions. The method further includes producing an image of the test structures. The method also includes performing image analysis of the image to recognize a position with an extreme of a gray level. In addition, the method includes calculating an overlay error according to the recognized position.

Abstract: An alternating layer stack of insulating layers and sacrificial material layers is formed over a semiconductor substrate, and memory stack structures are formed through the vertically-alternating layer stack. A pair of unconnected barrier trenches or a moat trench is formed through the alternating stack concurrently with formation of backside trenches. Backside recesses are formed by isotropically etching the sacrificial material layers selective to the insulating layers while a dielectric liner covers the barrier trenches or the moat trench. A vertically alternating sequence of the insulating plates and the dielectric spacer plates is provided between the pair of barrier trenches or inside the moat trench. Electrically conductive layers are formed in the backside recesses. A first conductive via structure is formed through the vertically alternating sequence concurrently with formation of a second conductive via structure through a dielectric material portion adjacent to the alternating stack.

Abstract: Field effect transistor and manufacturing method thereof are disclosed. Field effect transistor includes a substrate, a fin, spacers, a gate structure, a hard mask pattern, an insulating layer, and a gate contact. The fin protrudes from the substrate and extends in a first direction. The spacers run in parallel over the fin and extending in a second direction perpendicular to the first direction. The gate structure extends between the spacers and covers the fin. The hard mask pattern covers the gate structure and extends in between the spacers. The insulating layer is disposed over the substrate and covers the hard mask pattern, the gate structure and the spacers. The gate contact penetrates the insulating layer and physically contacts the gate structure. A bottom surface of the gate contact is coplanar with top surfaces of the spacers and the hard mask pattern.

Abstract: An image sensor and a method for fabricating the image sensor are provided. In the method for fabricating the image sensor, at first, a substrate having a first surface and a second surface opposite to the first surface is provided. Then, light-sensitive regions are formed in the substrate. Thereafter, transfer gate structures are formed on the first surface of the substrate. Then, the first surface of the substrate is formed to form recess structures on the light-sensitive regions. Thereafter, light-reflective layers are formed to cover the recess structures of the first surface of the substrate, in which the recess structures are filled with protrusion structures of the light-reflective layers. Further, the second surface of the substrate may be etched to form recess structures corresponding to the light-sensitive regions.

Abstract: Semiconductor devices and methods of manufacturing semiconductor devices with differing threshold voltages are provided. In embodiments the threshold voltages of individual semiconductor devices are tuned through the removal and placement of differing materials within each of the individual gate stacks within a replacement gate process, whereby the removal and placement helps keep the overall process window for a fill material large enough to allow for a complete fill.

Abstract: A semiconductor device includes a first die embedded in a molding material, where contact pads of the first die are proximate a first side of the molding material. The semiconductor device further includes a redistribution structure over the first side of the molding material, a first metal coating along sidewalls of the first die and between the first die and the molding material, and a second metal coating along sidewalls of the molding material and on a second side of the molding material opposing the first side.

Abstract: Methods and apparatus for use in the manufacture of a display element. Some embodiments include a method for selective pick up of a subset of a plurality of electronic devices adhered to a handle layer. The method comprises modifying a level of adhesion between one or more electronic devices of the plurality of electronic devices adhered to the handle layer, such that the subset of the plurality of electronic devices has a level of adhesion to the handle layer that is less than a force applied by a pick up tool, PUT. This enables selective pick up of the subset of the plurality of electronic devices from the handle layer by the PUT.

Abstract: A protective film composition includes a polymer having the following formula: each of a, b, and c is a mole fraction; a+b+c=1; 0.05?a/(a+b+c)?0.3; 0.1?b/(a+b+c)?0.6; 0.1?c/(a+b+c)?0.6; each of R1, R2, and R3 is a hydrogen atom or a methyl group; R4 is a hydrogen atom, a butyrolactonyl group, or a substituted or unsubstituted C3 to C30 alicyclic hydrocarbon group; and R5 is a substituted or unsubstituted C6 to C30 linear or cyclic hydrocarbon group. A method of manufacturing a semiconductor package includes forming a sawing protective film on a semiconductor structure by using the protective film composition and sawing the sawing protective film and the semiconductor structure from the sawing protective film.

Abstract: A 3D memory device includes a multi-layers stacking structure having an O-shaped opening; a memory structure layer having a first string portion and a second string portion disposed on two opposite sides of a sidewall of the O-shaped opening and a connection portion disposed on a bottom of the O-shaped opening and connecting the first and the second string portion; a dielectric pillar disposed in the O-shaped opening and over the connection portion; an isolation body extending along a direction and embedded among the first string portion, the second string portion and the connection portion to isolate the first string portion from the second string portion; a first contact disposed in a first recess defined by the first string portion, the dielectric pillar and the isolation body; and a second contact disposed in a second recess defined by the second string portion, the dielectric pillar and the isolation body.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a semiconductor chip including a substrate having a first surface and a second surface arranged opposite to the first surface; at least one stress-decoupling trench that extends from the first surface into the substrate, where the at least one stress-decoupling trench extends partially into the substrate towards the second surface although not completely to the second surface; a microelectromechanical systems (MEMS) element, including a sensitive area, disposed at the first surface of the substrate and laterally spaced from the at least one stress-decoupling trench; and a stress-decoupling material that fills the at least one stress-decoupling trench and covers the sensitive area of the MEMS element.

Abstract: An integrated circuit (IC) chip carrier includes one or more memory devices therein. The memory is integrated into the carrier prior to the IC chip being connected to the carrier. Therefore, the IC chip may be connected to the memory at the same time as the IC chip is connected to the carrier. An access instruction may be sent from the IC chip to the memory through a wiring line of the IC chip carrier. Power potential may be sent from a system board to the memory through a vertical interconnect access (VIA). Alternatively, an access instruction may be sent from a first IC chip to the memory and power potential may be sent from a second IC chip to the memory.

Abstract: The present disclosure provides a method for fabricating an integrated circuit device. The method includes providing a precursor including a substrate having first and second metal-oxide-semiconductor (MOS) regions. The first and second MOS regions include first and second gate regions, semiconductor layer stacks, and source/drain regions respectively. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the first gate region to form first outer oxide layer and inner nanowire set, and exposing the first inner nanowire set. A first high-k/metal gate (HK/MG) stack wraps around the first inner nanowire set. The method further includes laterally exposing and oxidizing the semiconductor layer stack in the second gate region to form second outer oxide layer and inner nanowire set, and exposing the second inner nanowire set. A second HK/MG stack wraps around the second inner nanowire set.

Abstract: Methods and apparatuses for forming symmetrical spacers for self-aligned multiple patterning processes are described herein. Methods include depositing gapfill material by atomic layer deposition over a patterned substrate including core material and a target layer, planarizing substrate, and etching the core material to form symmetrical spacers. Gapfill material may be deposited for a duration insufficient to completely fill features such that features are underfilled.

Abstract: Provided is a light-emitting device and a method for manufacturing the same which avoid a distinct color unevenness during the light emission even if variations are present among the light-emitting elements in the concentration of the phosphor that precipitates in the resin for sealing the light-emitting elements. The light-emitting device includes a substrate, a plurality of light-emitting elements that are mounted on the substrate, a first resin layer that integrally seals the light-emitting elements and includes a first phosphor that is excited by light from the light-emitting elements at a concentration that is high as it goes to a lower end near the substrate from an upper end distant from the substrate, and a second resin layer that is provided at an upper side of the first resin layer and includes a second phosphor that is excited by light from the light-emitting elements at a uniform concentration.

Abstract: A semiconductor device includes a first substrate including a first surface, at least one first bonding pad disposed on the first surface, and at least one second bonding pad disposed on the first surface. The first bonding pad includes a first width, and the second bonding pad includes a second width. The second width is substantially different from the first width.

Abstract: A quantum dot has a property that, when subjected to a GC-MS qualitative analysis at 350° C., octadecene (ODE) is present while oleylamine (OLA) is absent. A light emitting apparatus has a fluorescent layer covering and disposed immediately above a light emitting side of a light emitting device. The fluorescent layer, which is disposed immediately above the light emitting device, is formed of a resin with quantum dots dispersed therein. Deteriorations of light emission intensities at respective RGB peak wavelengths of the light emitting device after light emission for 1000 hours at 85° C. are all within 30% of a light emission intensity of the light emitting device before the light emission. Black discoloration caused by the deteriorations of the light emission intensities at the respective RGB peak wavelengths of the light emitting device does not occur in the resin.

Abstract: A display device includes a substrate, a light-emitting member, and an anti-reflective glass layer. The light-emitting member is on the substrate. The anti-reflective glass layer is over the light-emitting member, and the anti-reflective glass layer has a transmittance of 40-95%. The anti-reflective glass layer includes a glass layer and a light-absorbing layer. The glass layer has a rough top surface and a haze of 70-80%. The light-absorbing layer is on the rough top surface of glass layer.

Abstract: A method of manufacturing a light-emitting element includes: providing a wafer including: a substrate, and a semiconductor structure; forming a plurality of modified regions inside the substrate of the wafer by irradiating the substrate with a laser beam; and separating the wafer into a plurality of light-emitting elements after said irradiating the substrate with the laser beam. Said forming the plurality of modified regions includes: scanning the laser beam along a plurality of first lines, the plurality of first lines extending in a first direction and being arranged in a second direction, the first direction being parallel to the first surface, the second direction intersecting the first direction and being parallel to the first surface, and scanning the laser beam along a plurality of second lines, the plurality of second lines extending in the second direction and being arranged in the first direction.

Abstract: Systems and methods of detecting marine seismic survey parameters are provided. A data processing system can obtain seismic data from seismic data acquisition units disposed on a seabed responsive to an acoustic signal propagated from an acoustic source through a water column. The data processing system can determine from the seismic data, a direct arrival time for the acoustic signal at each of the plurality of seismic data acquisition units, and can obtain an estimated depth value of each of the plurality of seismic data acquisition units and an estimated water column transit velocity of the acoustic signal. The data processing system can apply a depth model and a water column transit velocity model to the estimated depth value and to the estimated water column transit velocity determine an updated depth value and an updated water column transit velocity for each of the plurality of seismic data acquisition units.