Abstract: The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first semiconductor structure, a first connecting structure, and a second semiconductor structure positioned on the first connecting structure. The first connecting structure includes a first connecting insulating layer positioned on the first semiconductor structure, two first conductive layers positioned in the first connecting insulating layer, and a first porous layer positioned between the two first conductive layers. The second semiconductor structure is positioned on the first connecting structure and includes two second conductive features positioned on the two first conductive layers. The first conductive layer has a first width, the second conductive feature has a second width greater than the first width, and the different width forms a step-shaped cross-sectional profile near an interface of the first conductive layer and the second conductive feature.

Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.

Abstract: In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure being electrically connect to the integrated circuit die, the redistribution structure including a pad; a passive device including a conductive connector physically and electrically connected to the pad; and a protective structure disposed between the passive device and the redistribution structure, the protective structure surrounding the conductive connector, the protective structure including an epoxy flux, the protective structure having a void disposed therein.

Abstract: Aspects of the present disclosure are directed to systems, method, and structures including a high-resolution shadow mask with tapered aperture/pixel openings that advantageously overcomes problems plaguing the prior art namely shadowing, sagging, and fragility.

Abstract: A barrier free quantum dot particles film includes a free standing layer comprising shielded quantum dot particles; wherein the shielded quantum dot particles are formed by shielding quantum dot particles by at least one shielding method; wherein the shielded quantum dot particles are characterized in resisting at least one condition selected from the group consisting of high temperature, high humidity and water; and wherein the shielded quantum dot particles are dispersed in an acrylate adhesive. A method of fabricating a barrier free quantum dot particles free standing film is also disclosed. The method of fabrication of shielded quantum dot particles film on a light emitting diode (LED) lens is also disclosed.

Abstract: There is provided a method for producing, on one same wafer, at least one first transistor surmounted at least partially on a voltage stressed layer and a second transistor surmounted at least partially on a compression stressed layer, the method including providing a wafer including the first and the second transistors; forming at least one stressed nitride-based layer, on the first and the second transistors, the layer being voltage stressed; depositing a protective layer so as to cover a first zone of the layer, the first zone covering at least partially the first transistor and leaving a second zone of the layer uncovered, the second zone at least partially covering the second transistor; and modifying a type of stress of the second zone of the layer by implanting hydrogen-based ions from a plasma in the second zone, such that the second zone of the layer is compression stressed.

Abstract: A first semiconductor die and a second semiconductor die can be bonded in a manner that enhances alignment of bonding pads. Non-uniform deformation of a first wafer including first semiconductor dies can be compensated for by forming a patterned stress-generating film on a backside of the first wafer. Metallic bump portions can be formed on concave surfaces of metallic bonding pads by a selective metal deposition process to reduce gaps between pairs of bonded metallic bonding pads. Pad-to-pad pitch can be adjusted on a semiconductor die to match the pad-to-pad pitch of another semiconductor die employing a tilt-shift operation in a lithographic exposure tool. A chuck configured to provide non-uniform displacement across a wafer can be employed to hold a wafer in a contoured shape for bonding with another wafer in a matching contoured position. Independently height-controlled pins can be employed to hold a wafer in a non-planar configuration.

Abstract: A capacitor includes a first electrode, a second electrode facing the first electrode, and a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes. The dielectric layer has a thickness of 10 nm or more. The first electrode contains carbon. At the interface between the dielectric layer and the first electrode, an elemental percentage of carbon is 30 atomic % or less.

Abstract: The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.

Abstract: A semiconductor package includes a mold substrate, at least one semiconductor chip disposed in the mold substrate and including chip pads, and a redistribution wiring layer covering a first surface of the mold substrate and including a first redistribution wiring and a second redistribution wiring stacked in at least two levels to be electrically connected to the chip pads. The first redistribution wiring includes a signal line extending in a first region, and the second redistribution wiring includes a ground line in a second region overlapping with the first region. The ground line has a plurality of through holes of polygonal column shapes.

Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming a first semiconductor fin and a second semiconductor fin over a semiconductor substrate. The second semiconductor fin is wider than the first semiconductor fin. The method also includes forming a gate stack over the semiconductor substrate, and the gate stack extends across the first semiconductor fin and the second semiconductor fin. The method further includes forming a first source/drain structure on the first semiconductor fin, and the first source/drain structure is p-type doped. In addition, the method includes forming a second source/drain structure on the second semiconductor fin, and the second source/drain structure is n-type doped.

Abstract: A method for the temporary bonding of a substrate of interest to a handle substrate, comprising a step of forming an assembly by placing the bonding faces of the substrate of interest and of the handle substrate into contact with one another via a thermoplastic polymer, and a step of treating the assembly at a treatment temperature that exceeds the glass transition temperature of the thermoplastic polymer. Prior to the assembly forming step, this method comprises: a step of producing, at the bonding face of one of either the substrate of interest or the handle substrate, a central cavity surrounded by a peripheral ring made of a material that is rigid at the treatment temperature, and a step of forming a layer of the thermoplastic polymer filling the central cavity.

Abstract: A light-emitting device package is provided. The light-emitting device package includes: a substrate having a first surface and a second surface, and having a first opening and a second opening spaced apart from each other; a light-emitting structure disposed on the first surface of the substrate and vertically overlapping the first opening; and an image sensor including a photoelectric conversion region, the photoelectric conversion region being disposed in the substrate and vertically overlapping the second opening. Light from the light-emitting structure is emitted toward the second surface of the substrate through the first opening.

Abstract: A method is provided for the manufacture of an integrated semiconductor device that includes an embedded flash memory array formed in a recessed region of a semiconductor substrate, the method includes, prior to formation of floating and control gate stacks of the memory array, depositing a protective layer over layers of gate material, and depositing a self-leveling sacrificial layer over the protective layer to produce a substantially planar upper surface. The sacrificial layer is then etched to a depth that removes the sacrificial layer and leaves a substantially planar face on the protective layer. A photo mask is then deposited on the protective layer and the gate stacks are etched from the layers of gate material.

Abstract: Apparatus and methods for generating a flow of radicals are provided. An ion blocker is positioned a distance from a faceplate of a remote plasma source. The ion blocker has openings to allow the plasma to flow through. The ion blocker is polarized relative to a showerhead positioned on an opposite side of the ion blocker so that there are substantially no plasma gas ions passing through the showerhead.

Abstract: A method of manufacturing a display device, the method including providing a substrate, forming a first electrode, a second electrode spaced from the first electrode and in a same plane as the first electrode, a first alignment line connected to the first electrode, and a second alignment line connected to the second electrode on the substrate, self-aligning the plurality of light emitting elements by providing a solution containing a plurality of light emitting elements on the substrate, removing the first alignment line and the second alignment line from the substrate on which the plurality of light emitting elements are self-aligned, forming a first contact electrode electrically connecting one end of each light emitting element to the first electrode, and forming a second contact electrode electrically connecting an other end of each light emitting element to the second electrode.

Abstract: A photoelectric conversion element capable of reducing a specific dark current. In a photoelectric conversion element (10) including an anode (12), a cathode (16), and an active layer (14) provided between the anode and the cathode, the active layer contains a p-type semiconductor material having a band gap of 0.5 eV to 1.58 eV, and an n-type semiconductor material, the n-type semiconductor material is a C60 fullerene derivative, and on an image obtained by binarizing an image of the active layer observed by a transmission electron microscope, the junction length between a phase of the n-type semiconductor material and a phase of the p-type semiconductor material is 120 ?m to 170 ?m per square micrometer of the area of the binarized image.

Abstract: In a method of designing a mask, a first mask including an active region, a gate structure, and a gate tap partially overlapping the active region and the gate structure is designed. The first mask is changed so that a portion of the gate tap is extended. An OPC is performed on the changed first mask to design a second mask.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an active pattern, a gate electrode extending in a first direction and crossing the active pattern which extends in a second direction, a separation structure crossing the active pattern and extending in the first direction, a first gate dielectric pattern disposed on a side surface of the gate electrode, a second gate dielectric pattern disposed on a side surface of the separation structure, and a gate capping pattern covering a top surface of the gate electrode. A level of a top surface of the separation structure is higher than a level of a top surface of the gate capping pattern.

Abstract: A semiconductor device manufacturing method includes forming an organic insulating layer on a semiconductor on which metal wiring is provided, the organic insulating layer having an opening to expose part of the metal wiring, forming a seed metal covering the part of the metal wiring exposed from the opening, and an inside face and an around portion of the opening of the organic insulating layer, forming a mask covering an edge of the seed metal and exposing part of the seed metal formed in the opening, and forming a barrier metal on the seed metal exposed from the mask by electroless plating. The mask includes an organic material or an inorganic dielectric material.