Abstract: A storage apparatus is provided that is capable of reducing data maintenance management costs with a performance that is both highly reliable and fast. The present invention is storage apparatus where an intermediary device is arranged between a controller and a plurality of disk devices of different performances arranged in a hierarchical manner. The controller unit carries out I/O accesses to and from the disk devices via the intermediary devices based on access requests sent from host apparatus. The intermediary device includes a power saving control function for the disk device and carries out operation control such as spin off and spin up of disk devices in accordance with conditions set in advance.

Abstract: A computer main unit and a PCI_Box (#0) are connected to each other in a loop connection manner by two paths. A first path is formed of an SMBus and a PCI_Box connection cable and a second path is formed of another PCI_Box connection cable. A monitoring and control unit (MMB) recognizes a connection path by reading out, through the second path, connection setting information written to the PCI_Box (#0) via the first path.

Abstract: A method and apparatus enables users to specify analog connections for devices on a data bus network such as an IEEE 1394 network in a convenient, time-efficient manner. According to an exemplary embodiment, the method includes steps of enabling an on-screen display comprising a list of devices connected to the digital data bus network requiring analog connections to the apparatus, and enabling a user to specify the analog connections responsive to the on-screen display.

Abstract: A system that facilitates maintaining hard disk drive performance comprises a memory component that includes extensions to at least one protocol associated with a hard disk drive, the extensions enable communications to occur in real-time between an operating system and the hard disk drive. An interface component utilizes the extensions to receive a notification from the hard disk drive and relay the notification to the operating system, the notification relates to an operating parameter of the hard disk drive.

Abstract: A controller including an interface module and an index module. The interface module is configured to connect devices. The index module is configured to include, in a table stored in memory, an entry for each of the devices. Each entry includes an address field. The index module is configured to: receive a frame of data including an address of one of the devices; compare the address to the address fields associated with the entries in the table; in response to the address matching one of the address fields, access an index value identifying an entry of the table when the address matches one of the address fields; and in response to the address not matching one of the address fields, generate the index value. The index value is used to connect the device associated with the matching one of the address fields with the one of the devices.

Abstract: A Direct Memory Access controller controls access to memory in a data processing system via a system bus. The controller is made up of a data load unit configured for performing load operations with data. A data computation unit is configured for performing data conversion and is pipeline connected in sequence to the data load unit. A data store unit is also pipeline connected in sequence to the data computation unit and is configured for performing burst store operations onto a system bus for storage in system memory.

Abstract: A system for I/O controller-processor interconnect coupling supporting a push-pull DMA read operation, in one aspect, may comprise a processor interconnect comprising a plurality of caches and memory subsystems and an I/O controller coupled with the processor interconnect. The I/O controller may comprise a plurality of DMA read request queues, a DMA read slot pool comprising a plurality of DMA read slots, and an expander logic determining a priority of requests in said request queues.

Abstract: Disclosed is a signal input system to input an image signal from source equipment to sink equipment through a High Definition Multimedia Interface, wherein the source equipment comprises a transmission section to transmit a format signal to the sink equipment through a predetermined first line in the High Definition Multimedia Interface, the format signal having a voltage value corresponding to a format of the image signal and the sink equipment comprises: a reception section to receive the format signal transmitted through the first line by the transmission section; a judging section to judge the format of the image signal based on the voltage value of the format signal which is received by the reception section; and a setting section to set an image output based on a judgment result of the judging section.

Abstract: This invention makes it possible to automatically install the device driver of only an intended network device on a network. Pieces of identification information for temporarily recognizing partners are input in both a client terminal and a network compliant device corresponding to a driver to be installed. When the identification information is input, the network compliant device multicasts a Hello message which describes the identification information and is necessary to enter the network. The client terminal receives the Hello message, and when information which matches the input identification information is described in the Hello message, shifts to a process based on UPnP. When the client terminal receives a Hello message not containing any description which matches the identification information, it does not notify the OS of the message.

Abstract: An interface device is associated with a local device. The interface device is configured to process payload data messages among the local device and peer devices. The payload data messages encapsulated according to a particular protocol. In at least one of the local device and the interface device, configuration messages are generated. The configuration messages are communicated among the local device and the interface device, the configuration messages associated with configuring the operation of the local device and the interface device with respect to the payload data messages.

Abstract: In a first aspect, a first method is provided for servicing commands. The first method includes the steps of (1) receiving a first command for servicing in a memory controller including a plurality of memory ports, wherein the first command is of a first priority; (2) receiving a second command for servicing in the memory controller, wherein the second command is of a second priority that is higher than the first priority; (3) determining whether the first and second commands will be serviced through the same memory port; and (4) if the first and second commands will not be serviced through the same memory port, servicing the first and second commands during the same time period. Numerous other aspects are provided.

Abstract: A microprocessor for processing instructions comprises multiple clusters for receiving the instructions, each of the clusters having a plurality of functional units for executing the instructions, multiple register sub-files each having multiple registers for storing data for executing the instructions, wherein each of the clusters is associated with corresponding one of the register sub-files so that an instruction dispatched to a cluster is executed by accessing registers in a register sub-file associated with the cluster to which the instruction is dispatched, a register-renaming unit for renaming target registers in an instruction with registers in a register sub-file associated with a cluster to which the instruction is dispatched, and issue-queue units each of which is associated with a corresponding one of the clusters, wherein an issue-queue unit holds instruction renamed by the register-renaming unit until the renamed instruction is issued to be executed in a cluster associated with the issue-queue u

Abstract: The present invention provides mechanisms that enable application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local operating system or hypervisor. In one aspect of the present invention, a mechanism is provided for handling user space creation and deletion operations for creating and deleting allocations of linear block addresses of a physical storage device to application instances. For creation, it is determined if there are sufficient available resources for creation of the allocation. For deletion, it is determined if there are any I/O transactions active on the allocation before performing the deletion. Allocation may be performed only if there are sufficient available resources and deletion may be performed only if there are no active I/O transactions on the allocation being deleted.

Abstract: Techniques are described that can be used to support integrity validation of protocol data units. An iSCSI compatible logic may establish a memory region to store a header portion of the protocol data unit. In some implementations, the iSCSI compatible logic may read the header and determine a size of a second memory region to store a payload portion of the protocol data unit. In some implementations, the iSCSI compatible logic may set the second memory region as a maximum possible size of the payload portion. TCP compatible logic may include the capability to validate an integrity of the header or data portions of the protocol data unit. TCP compatible logic may request data mover logic to determine an integrity validation value for a header and/or data portion of the protocol data unit in the process of copying the protocol data unit to among the memory region or the second memory region.

Abstract: A host station and a scatter gather engine (SGE) station communicate with each other. In the host station, a host generation indication is maintained. In the SGE station, an SGE generation indication is maintained. Information, including the host generation indication maintained in the host station, is written into an entry of a data structure in a memory associated with the host station. In the SGE station, information is received from each of at least one of the entries of the data structure. The received information is processed, including comparing the SGE generation indication maintained in the SGE station to the host generation indication in the entry to determine whether the information in that entry includes valid information.

Abstract: An operation apparatus includes a sequencer controlling states of a plurality of operation devices and a configuration memory storing therein configuration information as setting information for each state in the operation device. In the operation apparatus, a path which requires a data buffer and another path which requires no such a data buffer are provided for inputting data to the operation device, a data buffer control part is provided for controlling selection from these two paths and operation of the data buffer, and contents of path selection and operation control of the data buffer carried out by the data buffer control part are set according to the configuration information.

Abstract: A processor implements conditional vector operations in which, for example, an input vector containing multiple operands to be used in conditional operations is divided into two or more output vectors based on a condition vector. Each output vector can then be processed at full processor efficiency without cycles wasted due to branch latency. Data to be processed are divided into two groups based on whether or not they satisfy a given condition by e.g., steering each to one of the two index vectors. Once the data have been segregated in this way, subsequent processing can be performed without conditional operations, processor cycles wasted due to branch latency, incorrect speculation or execution of unnecessary instructions due to predication. Other examples of conditional operations include combining one or more input vectors into a single output vector based on a condition vector, conditional vector switching, conditional vector combining, and conditional vector load balancing.

Abstract: A bus apparatus for transferring information between a bus master and a bus slave includes a plurality of pipeline registers capable of transmitting information from the bus master to the bus slave by a pipeline processing; and a plurality of management devices that manage each pipeline register. Also, the management device includes: a holding state keeping unit that keeps a holding state as information indicating whether a current stage's pipeline register corresponding to the management device holds information; an adjacent stage's holding state specifying unit that specifies the holding state of a previous stage's pipeline register that transmits information to the current stage's pipeline register and the holding state of a subsequent stage's pipeline register to which information from the current stage's pipeline register is transmitted; and a transfer control unit that determines whether information held by the corresponding pipeline register is transferred.

Abstract: A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Abstract: A computer main unit and a PCI_Box (#0) are connected to each other in a loop connection manner by two paths. A first path is formed of an SMBus and a PCI_Box connection cable and a second path is formed of another PCI_Box connection cable. A monitoring and control unit (MMB) recognizes a connection path by reading out, through the second path, connection setting information written to the PCI_Box (#0) via the first path.